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Date: Mon, 19 Oct 2020 15:38:59 -0700
From: Anthony Martin <ality@pbrane.org>
To: 9front@9front.org
Subject: Re: 9FRONT "EMAILSCHADEN" RELEASED
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sl@stanleylieber.com once said:
> pc, pc64: remove mystery "type" bits in pcicfgrw*raw() (fixes qemu, tha=
nks mischief)

In changeset 78891f472fbf, cinap wrote:

	the access functions for pci config space in config mode #1
	used to set bit 0 in the register offset if the access was
	to a device on any bus different from 0.

	it is completely unclear why this was done and i can't find
	any documentation on this.

	but for sure, this breaks all pci config spacess access to
	pci devices behind a bridge on qemu. with -trace pci* it
	was discovered that all config space register offsets on
	devies behind pci brige where off by one.

Our code looks like it was a slight misreading of the specification
and the change looks good. However, the original behavior should have
been innocuous for any conforming host bridge:

	For Type 1 translations, the host bridge directly copies the
	contents of the CONFIG_ADDRESS register (excluding bits 31 and
	0) onto the PCI AD lines during the address phase of a
	configuration transaction making sure that AD[1::0] is "01".

	(from PCI Local Bus Specification, Revision 3.0, =C2=A73.2.2.3.2)

Note the phrase "excluding bits 31 and 0". Also, the PCI-PCI bridge
in QEMU should be doing a Type 1 to Type 0 translation before the
device behind the bridge sees the address.

Cheers,
  Anthony