From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=0.2 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED autolearn=no autolearn_force=no version=3.4.4 Received: (qmail 7801 invoked from network); 12 Nov 2022 02:34:35 -0000 Received: from 9front.inri.net (168.235.81.73) by inbox.vuxu.org with ESMTPUTF8; 12 Nov 2022 02:34:35 -0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received: from mail-pl1-f169.google.com ([209.85.214.169]) by 9front; Fri Nov 11 21:33:20 -0500 2022 Received: by mail-pl1-f169.google.com with SMTP id b21so5618280plc.9 for <9front@9front.org>; Fri, 11 Nov 2022 18:33:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mforney.org; s=google; h=subject:date:to:from:message-id:from:to:cc:subject:date:message-id :reply-to; bh=JXu1K56+qxg+ciSmOY6E8e8byRDeCFhLpbRK5MD+CQw=; b=BOMJOb43Io21ow7e0PUqvh0+obAnEm1f6qdDxwZpcfmRMTPAl7HsGQ2JPANkqQH28m oToi9TmmxhAz/JOsfZeEYu3c8etVPxsHhQ/HysQYtuxht8A9HQqxp8X/DnFOOu7l0NXi RTsZ33QJKqZs3Apj1VO+ozy2J93P7YZ1mIKB1NfYWPnih7cC/kSlysrjlkmKbP8QhsDQ EjY34WETOkWbgeARgzWxLBVB/NO01XkIyqgyT58c5yNKnQFytYLKx12f8OW4zaVdSker WFZKA1d6kFuHV8zB74LC7raXlnHTFMieHk9/2mFzRvZTGDIZUZ6kIpLzsIJcdYQPpRXh pyAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=subject:date:to:from:message-id:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JXu1K56+qxg+ciSmOY6E8e8byRDeCFhLpbRK5MD+CQw=; b=QMjrHoseRq75eL8fZiCtRnVhZ5fwZfjFeOqjm7lcp2ZxyylhV6kaWGtBgMyMejG20Z p+m/WwFK3TOXe8Czu+yJkvJC8LRUPb8iRYoibbpuI+8pu4JZecxK9J8iPeRuOIoPNawI 87zG49aaHRg7onZ03NUedv+ad8jd+BZ3kzULqmGZmsafOCMMeDjGKBw80YD1eGl/nvlT T1nz6K+gRTc/4hTqEyIzGAuFljKAYiGB6f7bWGTOfliiFOSP9pNfrxTokfZh1DuXinNV Q27XNTgdKnnrRIeR4DJk4INuYwlDjq8IN33RjSGaqau6eNFmFHFqTEQImfQPnQnggPoq 8OHA== X-Gm-Message-State: ANoB5pn2vJE4dsYA/rH6yY0TGk4WQ3rl6BTO8MgQeCkfVQj/vsriLCxD EheKqgDbIBgG/42K0tMd1aOegxv+2u4FRheZKH8= X-Google-Smtp-Source: AA0mqf6msMv1UKUjUZlbcTWui0jfrkEx0c7rJxPz0GD8KRH4uE4/Rk8lrMxDkhhQ+WCG7PYU92rRHA== X-Received: by 2002:a17:902:ab58:b0:175:105a:3087 with SMTP id ij24-20020a170902ab5800b00175105a3087mr5258554plb.65.1668220395811; Fri, 11 Nov 2022 18:33:15 -0800 (PST) Return-Path: Received: from localhost ([2601:647:6400:20b0:cab2:9bff:fe88:d09c]) by smtp.gmail.com with ESMTPSA id s7-20020a170902a50700b00182d25a1e4bsm2375630plq.259.2022.11.11.18.33.14 for <9front@9front.org> (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Nov 2022 18:33:15 -0800 (PST) Message-ID: <636f05eb.170a0220.934c8.4131@mx.google.com> From: Michael Forney To: 9front@9front.org Date: Sat, 12 Nov 2022 01:11:09 +0000 List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: encrypted proxy WEB2.0 rails self-signing CMS module-based frontend Subject: [9front] [PATCH] usbxhci: wait for reset to complete before continuing initialization Reply-To: 9front@9front.org Precedence: bulk The xhci spec says that the HCRST bit is cleared once the reset is complete, and that no operational or runtime registers shall be written while the bit is set. Waiting for the reset to complete fixes initialization of some host controllers, such as the ASMedia ASM1142, which otherwise enter an endless init-recover loop. Also, add a comment about the reason for the 1ms delay. This appears to work around a system hang bug in intel chipsets through the 400 series (see errata 15 in [0]). [0] https://cdrdv2-public.intel.com/620856/620856-009.pdf --- I was trying to figure out why the two USB 3.1 ports on my system didn't work, and adding some debug prints in init() appeared to provide enough delay that it started working. I believe the root cause is not waiting for HCRST to clear, which is what xhci drivers in other operating systems do. diff a39eb30ffa2138a817bd787fdfd25eb65927e7d4 7fdb19aa0098ee41192d1a478db8dfed3514c706 --- a/sys/src/9/port/usbxhci.c +++ b/sys/src/9/port/usbxhci.c @@ -481,7 +481,10 @@ tsleep(&up->sleep, return0, nil, 10); ctlr->opr[USBCMD] = HCRST; + /* some intel controllers require 1ms delay after reset */ delay(1); + for(i=0; (ctlr->opr[USBCMD] & HCRST) != 0 && i<100; i++) + tsleep(&up->sleep, return0, nil, 10); for(i=0; (ctlr->opr[USBSTS] & (CNR|HCH)) != HCH && i<100; i++) tsleep(&up->sleep, return0, nil, 10);