From: kokamoto@hera.eonet.ne.jp
To: 9front@9front.org
Subject: Re: [9front] strange behaviour of igfx and vesa
Date: Thu, 23 Jun 2016 15:43:38 +0900 [thread overview]
Message-ID: <76c4ce1482a08c28b83f4e53b04127e8@titan.jitaku.localdomain> (raw)
In-Reply-To: <d3434e8516ba1b2240a2e0da6489bad7@felloff.net>
I checked out all the output from vesa driver, and found
no missed registeres in igfx.c not including treatments of
sotware flag registers.
Then, I turned the direction to find chip differences from the
programming manual. My chip belongs to DevBW, and
a working one to DevCL. I found DebBW difference in
registers of [6200][6204][6110][70030][70034][72180],
the last three are not used in G45 in igfx.c.
The [6200][6204] are not important, because we are getting
the right values from those usage.
Then, the [6110] register, adps register, is the cause, I suppose.
In page 93, the manual says, in the case of DevBW, to enable
the Analog display port, we must do a series of operations
in the right order like:
1) set bit #31 to 1, and [11:10] to "11"
2) wait for VSYNC
3) clear [11:10] to "00"
Yes, I see large wait loop for Vsync in vesa drivers output.
like:
wport ff00 00070024 # pipe A display status
rport ff04 00000000 # default value(no event)
wport ff04 00000002 # set to detect Vertical Blank Interrupt
wport ff00 00070024 # pipe A display status
rport ff04 00000000 # done above set
.....
wport ff00 00070024 # pipe A display status
rport ff04 00000000 # no event (default)
rport 0061 00 # PIT_CTL2
wport 0061 01 # PIT_CTL2
wport 0043 b6 # PIT_MODE
wport 0042 50 # PIT_CNTR2
wport 0042 05 # PIT_CNTR2
wport 0043 80 # PIT_MODE
rport 0042 33 # PIT_CNTR2
rport 0042 04 # PIT_CNTR2
wport 0043 80 # PIT_MODE
rport 0042 e3 # PIT_CNTR2
rport 0042 00 # PIT_CNTR2
wport 0043 80 # PIT_MODE
rport 0042 cb # PIT_CNTR2
rport 0042 02 # PIT_CNTR2
wport 0061 00 # PIT_CTL2
...
...
wport ff00 00070024 # pipe A display status
rport ff04 00000207 # State = Vsync occured, Start of VSYNC occured, VBLANK occured, Overlay Reg updated
However, there are output from/to many software flag registers
in this interval, I have been abondoned to deal with it, because
I have to investigate assembly codes. (sigh)
However, I got realized that the above 1) to 3) procedures
are not done in igfx.c. Therefore, I think this is our
problem. It may cause some large code rewriting.
How do you think?
Kenji
next prev parent reply other threads:[~2016-06-23 6:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-17 6:48 kokamoto
2016-06-17 12:46 ` [9front] " cinap_lenrek
2016-06-17 23:40 ` kokamoto
2016-06-18 1:29 ` kokamoto
2016-06-18 7:45 ` kokamoto
2016-06-18 23:38 ` kokamoto
2016-06-19 5:58 ` kokamoto
2016-06-20 2:48 ` kokamoto
2016-06-20 4:14 ` kokamoto
2016-06-22 0:25 ` kokamoto
2016-06-22 7:26 ` cinap_lenrek
2016-06-23 6:43 ` kokamoto [this message]
2016-06-23 10:55 ` cinap_lenrek
2016-06-23 11:24 ` kokamoto
2016-06-25 1:50 ` kokamoto
2016-06-30 2:06 ` kokamoto
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