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Date: Fri, 29 Jul 2016 10:15:40 +0200
From: cinap_lenrek@felloff.net
To: 9front@9front.org
Subject: Re: [9front] core-i5(TypeSNB) and vesa mode
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> It sounds like the same as I did here.

no, it is not. you put your code *before* the ivy bridge
fdi link code which works differently resulting in the
exeuction of patterns 2 followed by auto-train mode.
this enables the fdi with train pattern 2, not pattern 1
which is invalid.

also you poll the wrong interrupt register. you poll the
DEIIR (0x44008) which has bit definitions:

https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part2.pdf
section 2.5.1 "Display Engine Interrupt Registers Bit Definition"

bit 9:	Pipe_B_CRC_error;		This is an active high pulse on the Pipe B CRC error. 
bit 8:	Pipe_B_FIFO_underrun;	This is an active high level for the duration of the Pipe B FIFO underrun. 

	/* TypeSNB or TypeIVB */
		/* enable fdi */
		loadreg(igfx, p->fdi->rxtu[1]);
		loadreg(igfx, p->fdi->rxtu[0]);
		loadreg(igfx, p->fdi->rxmisc);
/* from here   K.Okamoto */
		if (igfx->type == TypeSNB){
			for(i=0;i<10;i++){	/* ensure Receive IIR, K.Okamoto */
				if(rr(igfx, 0x44008) & 1<<8)
				break;
			}
			p->fdi->rxctl.v &= ~(3<<8);	/* link train pattern 1 enable */
			p->fdi->rxctl.v |= (1<<8);		/* link train pattern 2 enable */
			p->fdi->rxctl.v |= 1<<31;	/* enable FDI pll */
			loadreg(igfx, p->fdi->rxctl);
			p->fdi->txctl.v &= ~(3<<8);	/* link train pattern 1 enable */
			p->fdi->txctl.v |= (1<<8);		/* link train pattern 2 enable */
			p->fdi->txctl.v |= 1<<31;	/* enable FDI pll */
			loadreg(igfx, p->fdi->txctl);
			for(i=0;i<10;i++){
				if(rr(igfx, 0x44008) & 1<<9)	/* ensure Receive IIR, K.Okamoto */
					break;
			}
/* to here  K.Okamoto */
		}
		p->fdi->rxctl.v &= ~(3<<8);	/* link train pattern 1 enable[default] */
		p->fdi->rxctl.v |= 1<<10;	/* auto train enable */
		p->fdi->rxctl.v |= 1<<31;	/* enable FDI pll */
		loadreg(igfx, p->fdi->rxctl);

		p->fdi->txctl.v &= ~(3<<8);	/* link train pattern 1 enable[default] */
		p->fdi->txctl.v |= 1<<10;	/* auto train enable */
		p->fdi->txctl.v |= 1<<31;	/* enable FDI pll */
		loadreg(igfx, p->fdi->txctl);

		/* wait for link training done */
		for(i=0; i<200; i++){
			sleep(5);
			if(rr(igfx, p->fdi->txctl.a) & 2)	/* auto train done */
				break;
		}
	
> I'm not interested now on it, because I have now another
> problem of stability of high resolution(up to 1680x1050x32

i cannot help you then.

> Kenji

--
cinap