From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from duke.felloff.net ([216.126.196.34]) by ewsd; Tue Oct 1 11:45:28 EDT 2019 Message-ID: <94879C18B19A72D7FF92E1D13AF96559@felloff.net> Date: Tue, 1 Oct 2019 17:45:20 +0200 From: cinap_lenrek@felloff.net To: 9front@9front.org Subject: Re: [9front] Kernel panic when setting screen resolution on machine with i810 chipset In-Reply-To: 4917D3F7013C68C4954F2DDCF94874DE@gmail.com MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: non-blocking proxy self-signing SOAP extension template the i81x driver appears to not take big pages into account (probably the driver predates the page size extension implementation). the offending code is here in i81xenable() in /sys/src/9/pc/vgai81x.c: /* * allocate space for the cursor data in system memory. * must be uncached. */ cursor = (ulong)xspanalloc(BY2PG, BY2PG, 0); mach0 = MACHP(0); pte = mmuwalk(mach0->pdb, cursor, 2, 0); if(pte == nil) panic("i81x cursor mmuwalk"); *pte |= PTEUNCACHED; scr->storage = cursor; xspanalloc() allocates memory in the kernel address space, which gets mapped with 4MB pages, not 4K pages. so the later attempt to manipulate the 4K pte to set the uncached bit fails (mmuwalk panics as theres no 4K pte). the proper way would be to write a function to uncache a kernel memory span that splits the 4MB mapping. for now, try to just comment out the 4 lines in i81xenable(): // pte = mmuwalk(mach0->pdb, cursor, 2, 0); // if(pte == nil) // panic("i81x cursor mmuwalk"); // *pte |= PTEUNCACHED; -- cinap