From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: * X-Spam-Status: No, score=1.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FROM,HTML_MESSAGE,RDNS_NONE autolearn=no autolearn_force=no version=3.4.4 Received: (qmail 14909 invoked from network); 6 Nov 2021 14:48:23 -0000 Received: from unknown (HELO 4ess.inri.net) (216.126.196.42) by inbox.vuxu.org with ESMTPUTF8; 6 Nov 2021 14:48:23 -0000 Received: from mail-lj1-f172.google.com ([209.85.208.172]) by 4ess; Sat Nov 6 10:39:12 -0400 2021 Received: by mail-lj1-f172.google.com with SMTP id 1so20072587ljv.2 for <9front@9front.org>; Sat, 06 Nov 2021 07:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=Y/ylM5voLzMapLyBwQrPfV1r/spN3JukNtc20k3Lu6s=; b=KEpcuEfQKQV6cDbg30pa8qeAmFUVMkEo+6RwaLAuCwJJWwFsUrHdLL9nONzBqd1dWt Lw12Ieykeo2Ty2PqVe+06yWSQc2+VpZOKEyyyvz9dJrUbmJe4HEp7hjhg9f5pXLnLrd2 SAwQu8IVw8IANrLh7jXWiFSAzK8XccHIHyFT2oiyI9rx+xm7w1a5nKhvaLks13gr7Zx6 7mlz06DfH747nlPxjL+Agxdw1hLFE4h01meqBcTt3aSgPjTj+mgtjUvOeBXYjdrvGq7+ d7oHTD0giAroUHCeqRs5wWEKjI8SZYy/6RsdA0t2hz/umqEQ12QGEZTeRQII+JmJHl0c 1eJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=Y/ylM5voLzMapLyBwQrPfV1r/spN3JukNtc20k3Lu6s=; b=fe/d116DaYly8Vi7aPpLwKemDVvWM/oj3IpqR7jXUO+wUho14D70aCQJxLYgiItY/T wns5nVPlRGgkNxFuBvQleUy1KIcDCCNsEXH8pQnpxiGHEStlkpbiEfFAMVKy3exKhWLV maGSXf8LUQZzy0KOJR3y22p9UZmtD/DKdurRoMfr5r08UrkPjpR2wlKH3++zvlGE1Li6 zw09pjBPzoz/wNUMUco1Ip0CWasQAZj/BSMn+Sv7xGtGOJtBC6dwtWQkLx1/WiHegTSh BOnp2GYD0dyrx52IcneRipIb28sbWIViQD6kOwMf4bE6lE2nf/5JzzuvH8jKIdMgtevO dgvg== X-Gm-Message-State: AOAM530dQBe2ox9He8JlNkWOTWrnlc9jmkfIK/p4cczd6t8brLQWmlZe bFCvdldVHvg8v52R4ceJXedrr/98rf3rn9IEOe8OBEZjmIQ= X-Google-Smtp-Source: ABdhPJw2jhDy1+VbbXHuJZRtHZl5089drgxHEjPEfVI/EREiJlea0IiQ7ZIND1YousuWjJJ7vrgt4Ua0pMH8QOVD2f4= X-Received: by 2002:a2e:b744:: with SMTP id k4mr68402844ljo.31.1636209116572; Sat, 06 Nov 2021 07:31:56 -0700 (PDT) MIME-Version: 1.0 References: <201AE9BC6F65A8E579C32A6761D6BD32@felloff.net> In-Reply-To: <201AE9BC6F65A8E579C32A6761D6BD32@felloff.net> From: joseph turco Date: Sat, 6 Nov 2021 10:31:44 -0400 Message-ID: To: 9front@9front.org Content-Type: multipart/alternative; boundary="0000000000002bf02205d01f9f30" List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: base metadata descriptor Subject: Re: [9front] pi 400 and cm4 mmc issues Reply-To: 9front@9front.org Precedence: bulk --0000000000002bf02205d01f9f30 Content-Type: text/plain; charset="UTF-8" Hey, if someone can guide me on how to use the the bootargs.c file (im assuming i have to build) i can test on my pi400 On Sat, Nov 6, 2021 at 5:13 AM wrote: > Mack Wallace sent me some kernel prints of the > emmc errors on raspberry pi 400 and cm4 compute module, > which look like this: > > sdhc: read error intr 2008002 stat 1fff0000 > > this means theres a DMA error there because bit 25 is set > in the interrupt status. > > checking the linux device tree, i found the following > comment: > > /* > * emmc2 has different DMA constraints based on SoC revisions. It was > * moved into its own bus, so as for RPi4's firmware to update them. > * The firmware will find whether the emmc2bus alias is defined, and if > * so, it'll edit the dma-ranges property below accordingly. > */ > emmc2bus: emmc2bus { > compatible = "simple-bus"; > #address-cells = <2>; > #size-cells = <1>; > ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; > dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; > emmc2: mmc@7e340000 { > compatible = "brcm,bcm2711-emmc2"; > reg = <0x0 0x7e340000 0x100>; > interrupts = ; > clocks = <&clocks BCM2711_CLOCK_EMMC2>; > status = "disabled"; > }; > }; > > this means the dram bus address for adma changes depending on the moon > phase and is only discoverable using the device tree blob. > > so i wrote the following patch, adding a *emmc2bus kernel parameter, > which we can eigther set manually, or will be discovered from the > device tree. > > the issue with device tree is that linux people like to pointlessly > re-arrange stuff all the time so it constantly breaks with firmware > updates. > > so first experiment is to apply the patches and see if we created > the *emmc2bus parameter like: > > cat '#ec/*emmc2bus' > > expected value should be eigther: c0000000 or 0 > > if the file isnt found, then my bootargs.c patch doesnt work. > > we can still manually override the offset by putting *emmc2bus=0 > in config.txt and then see if the mmc errors go away. > > anyone with a pi 400 or cm4 can try this out please? > > --- > /mnt/git/object/6c70026fa4b2ff235f60c883db15f55b4096bf6b/tree/sys/src/9/bcm/bootargs.c > +++ sys/src/9/bcm/bootargs.c > @@ -12,6 +12,7 @@ > static char *confval[MAXCONF]; > static int nconf; > static char maxmem[256]; > +static char emmc2bus[32]; > static char pciwin[38], pcidmawin[38]; > > static int > @@ -111,6 +112,15 @@ > len -= 3*4; > } > addconf("*maxmem", maxmem); > + } > + return; > + } > + if(strcmp(path, "/emmc2bus") == 0 && strcmp(key, "dma-ranges") == 0 > + && len == (2*4 + 2*4 + 1*4) && (beget4(p+2*4) | beget4(p+3*4)) == > 0){ > + if(findconf("*emmc2bus") < 0){ > + addr = (uvlong)beget4(p+0*4)<<32 | beget4(p+1*4); > + snprint(emmc2bus, sizeof(emmc2bus), "%llux", addr); > + addconf("*emmc2bus", emmc2bus); > } > return; > } > --- > /mnt/git/object/6c70026fa4b2ff235f60c883db15f55b4096bf6b/tree/sys/src/9/bcm64/sdhc.c > +++ sys/src/9/bcm64/sdhc.c > @@ -204,6 +204,7 @@ > ulong extclk; > int appcmd; > Adma *dma; > + uintptr busdram; > }; > > static Ctlr emmc; > @@ -247,7 +248,7 @@ > p->desc |= len< else > p->desc |= Maxdma< - p->addr = dmaaddr((void*)a); > + p->addr = emmc.busdram + (PADDR(a) - PHYSDRAM); > a += Maxdma; > len -= Maxdma; > n--; > @@ -293,7 +294,11 @@ > { > u32int *r; > ulong clk; > + char *s; > > + emmc.busdram = soc.busdram; > + if((s = getconf("*emmc2bus")) != nil) > + emmc.busdram = strtoul(s, nil, 16); > clk = getclkrate(ClkEmmc2); > if(clk == 0){ > clk = Extfreq; > @@ -507,7 +512,7 @@ > cachedwbse(buf, len); > else > cachedwbinvse(buf, len); > - WR(Dmadesc, dmaaddr(emmc.dma)); > + WR(Dmadesc, emmc.busdram + (PADDR(emmc.dma) - PHYSDRAM)); > okay(1); > } > > -- > cinap > --0000000000002bf02205d01f9f30 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hey, if someone can guide me on how to use the the bootarg= s.c file (im assuming i have to build) i can test on my pi400

=
On Sat, No= v 6, 2021 at 5:13 AM <cinap_= lenrek@felloff.net> wrote:
Mack Wallace sent me some kernel prints of the
emmc errors on raspberry pi 400 and cm4 compute module,
which look like this:

sdhc: read error intr 2008002 stat 1fff0000

this means theres a DMA error there because bit 25 is set
in the interrupt status.

checking the linux device tree, i found the following
comment:

=C2=A0/*
=C2=A0 * emmc2 has different DMA constraints based on SoC revisions. It was=
=C2=A0 * moved into its own bus, so as for RPi4's firmware to update th= em.
=C2=A0 * The firmware will find whether the emmc2bus alias is defined, and = if
=C2=A0 * so, it'll edit the dma-ranges property below accordingly.
=C2=A0 */
=C2=A0emmc2bus: emmc2bus {
=C2=A0compatible =3D "simple-bus";
=C2=A0#address-cells =3D <2>;
=C2=A0#size-cells =3D <1>;
=C2=A0ranges =3D <0x0 0x7e000000=C2=A0 0x0 0xfe000000=C2=A0 0x01800000&g= t;;
=C2=A0dma-ranges =3D <0x0 0xc0000000=C2=A0 0x0 0x00000000=C2=A0 0x400000= 00>;
=C2=A0emmc2: mmc@7e340000 {
=C2=A0compatible =3D "brcm,bcm2711-emmc2";
=C2=A0reg =3D <0x0 0x7e340000 0x100>;
=C2=A0interrupts =3D <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
=C2=A0clocks =3D <&clocks BCM2711_CLOCK_EMMC2>;
=C2=A0status =3D "disabled";
=C2=A0};
=C2=A0};

this means the dram bus address for adma changes depending on the moon
phase and is only discoverable using the device tree blob.

so i wrote the following patch, adding a *emmc2bus kernel parameter,
which we can eigther set manually, or will be discovered from the
device tree.

the issue with device tree is that linux people like to pointlessly
re-arrange stuff all the time so it constantly breaks with firmware
updates.

so first experiment is to apply the patches and see if we created
the *emmc2bus parameter like:

cat '#ec/*emmc2bus'

expected value should be eigther: c0000000 or 0

if the file isnt found, then my bootargs.c patch doesnt work.

we can still manually override the offset by putting *emmc2bus=3D0
in config.txt and then see if the mmc errors go away.

anyone with a pi 400 or cm4 can try this out please?

--- /mnt/git/object/6c70026fa4b2ff235f60c883db15f55b4096bf6b/tree/sys/src/9= /bcm/bootargs.c
+++ sys/src/9/bcm/bootargs.c
@@ -12,6 +12,7 @@
=C2=A0static char *confval[MAXCONF];
=C2=A0static int nconf;
=C2=A0static char maxmem[256];
+static char emmc2bus[32];
=C2=A0static char pciwin[38], pcidmawin[38];

=C2=A0static int
@@ -111,6 +112,15 @@
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 len -=3D 3*4;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 addconf("*maxmem", maxmem);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if(strcmp(path, "/emmc2bus") =3D=3D 0= && strcmp(key, "dma-ranges") =3D=3D 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0&& len =3D=3D (2*4 + 2*4 + 1*4) &&a= mp; (beget4(p+2*4) | beget4(p+3*4)) =3D=3D 0){
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if(findconf("*= emmc2bus") < 0){
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0addr =3D (uvlong)beget4(p+0*4)<<32 | beget4(p+1*4);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0snprint(emmc2bus, sizeof(emmc2bus), "%llux", addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0addconf("*emmc2bus", emmc2bus);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
--- /mnt/git/object/6c70026fa4b2ff235f60c883db15f55b4096bf6b/tree/sys/src/9= /bcm64/sdhc.c
+++ sys/src/9/bcm64/sdhc.c
@@ -204,6 +204,7 @@
=C2=A0 =C2=A0 =C2=A0 =C2=A0 ulong=C2=A0 =C2=A0extclk;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int=C2=A0 =C2=A0 =C2=A0appcmd;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 Adma=C2=A0 =C2=A0 *dma;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0uintptr busdram;
=C2=A0};

=C2=A0static Ctlr emmc;
@@ -247,7 +248,7 @@
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 p->desc |=3D len<<OLength | End | Int;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 else
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 p->desc |=3D Maxdma<<OLength;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0p->addr =3D dmaa= ddr((void*)a);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0p->addr =3D emmc= .busdram + (PADDR(a) - PHYSDRAM);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 a +=3D Maxdma;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 len -=3D Maxdma; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 n--;
@@ -293,7 +294,11 @@
=C2=A0{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u32int *r;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 ulong clk;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0char *s;

+=C2=A0 =C2=A0 =C2=A0 =C2=A0emmc.busdram =3D soc.busdram;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if((s =3D getconf("*emmc2bus")) !=3D = nil)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0emmc.busdram =3D st= rtoul(s, nil, 16);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 clk =3D getclkrate(ClkEmmc2);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if(clk =3D=3D 0){
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 clk =3D Extfreq; @@ -507,7 +512,7 @@
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cachedwbse(buf, len= );
=C2=A0 =C2=A0 =C2=A0 =C2=A0 else
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cachedwbinvse(buf, = len);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0WR(Dmadesc, dmaaddr(emmc.dma));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0WR(Dmadesc, emmc.busdram + (PADDR(emmc.dma) - P= HYSDRAM));
=C2=A0 =C2=A0 =C2=A0 =C2=A0 okay(1);
=C2=A0}

--
cinap
--0000000000002bf02205d01f9f30--