[9front] Anyone with a AMD chip with family 0fh or 10h?

[9front] Anyone with a AMD chip with family 0fh or 10h?

[Jacob Moody]

I recently poked around some of the cputemp code for the amd chips and
found some bits I'd like to improve but want to make sure someone can
test the changes.

Easy way to check:
; aux/cpuid | awk '/^typefam/ { print $3 }'

Looking for 0x0f and 0x10.


Thanks,
moody

Re: [9front] Anyone with a AMD chip with family 0fh or 10h?

[Jacob Moody]

On 2/22/25 20:50, Jacob Moody wrote:
> I recently poked around some of the cputemp code for the amd chips and
> found some bits I'd like to improve but want to make sure someone can
> test the changes.
> 
> Easy way to check:
> ; aux/cpuid | awk '/^typefam/ { print $3 }'
> 
> Looking for 0x0f and 0x10.
> 
> 
> Thanks,
> moody
> 


This work has expanded a bit and I've fleshed out support for more machines.
Anyone with families 0x10, 0x11, 0x12, 0x14, 0x15, 0x16, 0x17, 0x19, or 0x1a
is welcome to give it a try and report back. Some work has been committed
already so to apply you'll need a decently up to date machine.

So far it's been tested with: 0x17, 0x1a, 0x16
0x10 has only had minimal changes so I feel largely confident there.


diff acd2079ebf458c20ad5b3e5504c00a92d5fe46f1 uncommitted
--- a/sys/src/9/pc/cputemp.c
+++ b/sys/src/9/pc/cputemp.c
@@ -91,16 +91,14 @@
 	return t;
 }

+static Pcidev *amddev;
+
 static long
 amd0ftemprd(Chan*, void *a, long n, vlong offset)
 {
 	char *s, *e, buf[64];
 	long i, t, j, max;
-	Pcidev *p;

-	p = pcimatch(0, 0x1022, 0x1103);
-	if(p == nil)
-		return readstr(offset, a, n, "-1±-1 unsupported\n");
 	max = 2;
 	if(max > conf.nmach)
 		max = conf.nmach;
@@ -107,8 +105,8 @@
 	s = buf;
 	e = buf + sizeof buf;
 	for(j = 0; j < max; j++){
-		pcicfgw32(p, 0xe4, pcicfgr32(p, 0xe4) & ~4 | j<<2);
-		i = pcicfgr32(p, 0xe4);
+		pcicfgw32(amddev, 0xe4, pcicfgr32(amddev, 0xe4) & ~4 | j<<2);
+		i = pcicfgr32(amddev, 0xe4);
 		if(m->cpuidstepping == 2)
 			t = i>>16 & 0xff;
 		else{
@@ -125,39 +123,13 @@
 static long
 amd10temprd(Chan*, void *a, long n, vlong offset)
 {
-	char *s, *e, *r, *buf;
-	long i, t, c, nb, cores[MAXMACH];
-	Pcidev *p;
+	char buf[16];
+	u32int v;

-	nb = 0;
-	for(p = 0; p = pcimatch(p, 0x1022, 0x1203); ){
-		cores[nb++] = 1 + ((pcicfgr32(p, 0xe8) & 0x3000)>>12);
-		if(nb == nelem(cores))
-			break;
-	}
-	if(nb == 0)
-		return readstr(offset, a, n, "-1±-1 unsupported\n");
-	buf = smalloc(MAXMACH*4*32);
-	s = buf;
-	e = buf + MAXMACH*4*32;
-	nb = 0;
-	c = 0;
-	for(p = 0; p = pcimatch(p, 0x1022, 0x1203); nb++){
-		i = pcicfgr32(p, 0xa4) & 0x7fffffff;
-		i >>= 21;
-		t = i/8;
-		r = ".0";
-		if(i % 8 >= 4)
-			r = ".5";
-		/*
-		 * only one value per nb; repeat per core
-		 */
-		while(c++ < conf.nmach && cores[nb]--)
-			s = seprint(s, e, "%ld%s±0.5%s\n", t, r, "");
-	}
-	i = readstr(offset, a, n, buf);
-	free(buf);
-	return i;
+	v = pcicfgr32(amddev, 0xa4);
+	v = ((v>>21)+4) / 8;
+	snprint(buf, sizeof buf, "%ud±1\n", v);
+	return readstr(offset, a, n, buf);
 }

 static Pcidev*
@@ -167,11 +139,20 @@

 	for(p = nil; p = pcimatch(p, 0x1022, 0); )
 		switch(p->did){
-		case 0x1480:
+		case 0x1103:	/* 0f */
+		case 0x1203:	/* 10 */
+		case 0x1303:	/* 11 */
+		case 0x1703:	/* 14 */
+		case 0x1603:	/* 15 */
+		case 0x1403:
+		case 0x141d:
+		case 0x1533:	/* 16 */
+		case 0x1583:
+		case 0x1480:	/* 17 */
 		case 0x1450:
 		case 0x15d0:
 		case 0x1630:
-		case 0x14a4:
+		case 0x14a4:	/* 19 */
 		case 0x14b5:
 		case 0x14d8:
 		case 0x14eb:
@@ -180,8 +161,6 @@
 	return nil;
 }

-static Pcidev *snmdev;
-
 static u32int
 snmread(ulong addr)
 {
@@ -189,8 +168,8 @@
 	u32int v;

 	lock(&lk);
-	pcicfgw32(snmdev, 0x60, addr);
-	v = pcicfgr32(snmdev, 0x64);
+	pcicfgw32(amddev, 0x60, addr);
+	v = pcicfgr32(amddev, 0x64);
 	unlock(&lk);
 	return v;
 }
@@ -198,13 +177,15 @@
 static long
 amd17temprd(Chan*, void *a, long n, vlong offset)
 {
-	u32int i;
+	u32int v, r;
 	char buf[16];
+	enum { Range = 1u<<19, Tjsel = 1u<<17 };

-	i = snmread(0x59800);
-	i >>= 21;
-	i = (i+4)/8;
-	snprint(buf, sizeof buf, "%ud±1\n", i);
+	r = snmread(0x59800);
+	v = ((r >> 21)+4) / 8;
+	if(r & (Range|Tjsel))
+		v -= 49;
+	snprint(buf, sizeof buf, "%ud±1\n", v);
 	return readstr(offset, a, n, buf);
 }

@@ -216,20 +197,28 @@
 	if(intelcputempok())
 		return intelcputemprd;

-	if(strcmp(m->cpuidid,  "AuthenticAMD") == 0)
+	if(strcmp(m->cpuidid,  "AuthenticAMD") == 0){
+		amddev = finddev();
+		if(amddev == nil)
+			return nil;
 		switch(m->cpuidfamily){
 		case 0x0f:
 			return amd0ftemprd;
 		case 0x10:
+		case 0x11:
+		case 0x12:
+		case 0x14:
+		case 0x15:
+		case 0x16:
 			return amd10temprd;
 		case 0x17:
-			snmdev = finddev();
-			if(snmdev == nil)
-				return nil;
+		case 0x19:
+		case 0x1a:
 			return amd17temprd;
 		default:
 			return nil;
 		}
+	}

 	return nil;
 }

Re: [9front] Anyone with a AMD chip with family 0fh or 10h?

[Jacob Moody]

On 2/24/25 14:08, Jacob Moody wrote:
> On 2/22/25 20:50, Jacob Moody wrote:
>> I recently poked around some of the cputemp code for the amd chips and
>> found some bits I'd like to improve but want to make sure someone can
>> test the changes.
>>
>> Easy way to check:
>> ; aux/cpuid | awk '/^typefam/ { print $3 }'
>>
>> Looking for 0x0f and 0x10.
>>
>>
>> Thanks,
>> moody
>>
> 
> 
> This work has expanded a bit and I've fleshed out support for more machines.
> Anyone with families 0x10, 0x11, 0x12, 0x14, 0x15, 0x16, 0x17, 0x19, or 0x1a
> is welcome to give it a try and report back. Some work has been committed
> already so to apply you'll need a decently up to date machine.
> 
> So far it's been tested with: 0x17, 0x1a, 0x16
> 0x10 has only had minimal changes so I feel largely confident there.
> 
> 

My mail client seemed to have gargled the patch, use http://okturing.com/src/23588/body instead.

Re: [9front] Anyone with a AMD chip with family 0fh or 10h?

[adventures in9]

tested this, and it works with both a 17 and 19 family AMD cpu

thanks!

On Mon, Feb 24, 2025 at 3:02 PM Jacob Moody <moody@posixcafe.org> wrote:
>
> On 2/24/25 14:08, Jacob Moody wrote:
> > On 2/22/25 20:50, Jacob Moody wrote:
> >> I recently poked around some of the cputemp code for the amd chips and
> >> found some bits I'd like to improve but want to make sure someone can
> >> test the changes.
> >>
> >> Easy way to check:
> >> ; aux/cpuid | awk '/^typefam/ { print $3 }'
> >>
> >> Looking for 0x0f and 0x10.
> >>
> >>
> >> Thanks,
> >> moody
> >>
> >
> >
> > This work has expanded a bit and I've fleshed out support for more machines.
> > Anyone with families 0x10, 0x11, 0x12, 0x14, 0x15, 0x16, 0x17, 0x19, or 0x1a
> > is welcome to give it a try and report back. Some work has been committed
> > already so to apply you'll need a decently up to date machine.
> >
> > So far it's been tested with: 0x17, 0x1a, 0x16
> > 0x10 has only had minimal changes so I feel largely confident there.
> >
> >
>
> My mail client seemed to have gargled the patch, use http://okturing.com/src/23588/body instead.
>
>