From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=DATE_IN_PAST_24_48 autolearn=no autolearn_force=no version=3.4.4 Received: (qmail 14492 invoked from network); 30 Jan 2021 15:45:03 -0000 Received: from 1ess.inri.net (216.126.196.35) by inbox.vuxu.org with ESMTPUTF8; 30 Jan 2021 15:45:03 -0000 Received: from duke.felloff.net ([216.126.196.34]) by 1ess; Fri Jan 29 09:58:30 -0500 2021 Message-ID: Date: Fri, 29 Jan 2021 15:58:19 +0100 From: cinap_lenrek@felloff.net To: 9front@9front.org In-Reply-To: <0100017741afd09d-da43b097-8dba-46b2-98d9-05414e118708-000000@email.amazonses.com> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: JSON browser-scale enhancement Subject: Re: [9front] 9front on Raspberry Pi 400 Reply-To: 9front@9front.org Precedence: bulk ok, here we go. i wrote some code to extract the dma-rangles property from the device tree and apply it to the pci express code. this adds new kernel variables *pciwin and *pcidmawin, that reflect the setting. they get filled in by the device tree setting when booted from firmware, but can be overridden in cmdline.txt or when we /dev/reboot. new kernel images to try: http://felloff.net/usr/cinap_lenrek/9pi4-pciwin (image for sdcard) http://felloff.net/usr/cinap_lenrek/s9pi4-pciwin (kernel with debug symbols) sha1sums: 9b8775e9b9b9daebbd72cde308c2b7117d2d065b 9pi4 0a01ed1555e99f847ba9eab8e8693364d4839f2c s9pi4 what follows is a example bootmessage from my pi4 8GB. note that in your case, the *pcidmawin print below should be different. please report back what you get as output there. Plan 9 intrsoff: GIC intids [0-31]: 01ff0000 are locked in disable state intrsoff: GIC intids [0-31]: 0000ffff are locked in enable state cpu0: 1500MHz ARM Cortex-A72 r0p3 8102M memory: 998M kernel data, 7104M user, 31395M swap *pciwin: 0x600000000 0x604000000 *pcidmawin: 0x0 0xc0000000 pcienable PCI.0.0.0: pcr 0->7 pcienable PCI.1.0.0: pcr 0->2 bus dev type vid did intl memory 0 0/0 06 04 00 14e4 2711 0 ioa:00000000-00001000 4096 mema:600000000-600100000 1048576 ->1 1 0/0 0c 03 30 1106 3483 0 0:600000004 4096 #l0: genet: 1000Mbps port 0xFFFFFFFFBD580000 irq 189 ea dca632b1adfe usbxhci: cpu2: 1500MHz ARM Cortex-A72 r0p3 cpu3: 1500MHz ARM Cortex-A72 r0p3 cpu1: 1500MHz ARM Cortex-A72 r0p3 0x1106 0x3483: port 600000000 size 4096 irq 0 #l0: phy1 id 600d84a2 oui 80361 patch: diff -r 5c327eddc496 sys/src/9/bcm/bootargs.c --- a/sys/src/9/bcm/bootargs.c Sat Jan 23 20:36:09 2021 -0800 +++ b/sys/src/9/bcm/bootargs.c Fri Jan 29 15:45:16 2021 +0100 @@ -12,6 +12,7 @@ static char *confval[MAXCONF]; static int nconf; static char maxmem[256]; +static char pciwin[38], pcidmawin[38]; static int findconf(char *k) @@ -89,23 +90,23 @@ static void devtreeprop(char *path, char *key, void *val, int len) { + uvlong addr, size; + uchar *p = val; + char *s; + if((strcmp(path, "/memory") == 0 || strcmp(path, "/memory@0") == 0) && strcmp(key, "reg") == 0){ if(findconf("*maxmem") < 0 && len > 0 && (len % (3*4)) == 0){ - uvlong top; - uchar *p = val; - char *s; - - top = (uvlong)beget4(p)<<32 | beget4(p+4); - top += beget4(p+8); - s = seprint(maxmem, &maxmem[sizeof(maxmem)], "%#llux", top); + addr = (uvlong)beget4(p)<<32 | beget4(p+4); + addr += beget4(p+8); + s = seprint(maxmem, &maxmem[sizeof(maxmem)], "%#llux", addr); p += 3*4; len -= 3*4; while(len > 0){ - top = (uvlong)beget4(p)<<32 | beget4(p+4); - s = seprint(s, &maxmem[sizeof(maxmem)], " %#llux", top); - top += beget4(p+8); - s = seprint(s, &maxmem[sizeof(maxmem)], " %#llux", top); + addr = (uvlong)beget4(p)<<32 | beget4(p+4); + s = seprint(s, &maxmem[sizeof(maxmem)], " %#llux", addr); + addr += beget4(p+8); + s = seprint(s, &maxmem[sizeof(maxmem)], " %#llux", addr); p += 3*4; len -= 3*4; } @@ -113,6 +114,20 @@ } return; } + if(strncmp(path, "/scb/pcie@", 10) == 0 && len == (3*4 + 4*4)){ + p += 3*4; + addr = (uvlong)beget4(p)<<32 | beget4(p+4); + p += 2*4; + size = (uvlong)beget4(p)<<32 | beget4(p+4); + if(strcmp(key, "ranges") == 0 && findconf("*pciwin") < 0){ + snprint(pciwin, sizeof(pciwin), "%#llux %#llux", addr, addr+size); + addconf("*pciwin", pciwin); + } else if(strcmp(key, "dma-ranges") == 0 && findconf("*pcidmawin") < 0){ + snprint(pcidmawin, sizeof(pcidmawin), "%#llux %#llux", addr, addr+size); + addconf("*pcidmawin", pcidmawin); + } + return; + } if(strcmp(path, "/chosen") == 0 && strcmp(key, "bootargs") == 0){ if(len > BOOTARGSLEN) len = BOOTARGSLEN; diff -r 5c327eddc496 sys/src/9/bcm64/dat.h --- a/sys/src/9/bcm64/dat.h Sat Jan 23 20:36:09 2021 -0800 +++ b/sys/src/9/bcm64/dat.h Fri Jan 29 15:44:26 2021 +0100 @@ -249,7 +249,8 @@ uintptr physio; uintptr virtio; uintptr armlocal; - uintptr pciwin; + uintptr pciwin; /* PCI outbound window CPU->PCI */ + uintptr pcidmawin; /* PCI inbound window PCI->DRAM */ int oscfreq; }; extern Soc soc; diff -r 5c327eddc496 sys/src/9/bcm64/io.h --- a/sys/src/9/bcm64/io.h Sat Jan 23 20:36:09 2021 -0800 +++ b/sys/src/9/bcm64/io.h Fri Jan 29 15:43:55 2021 +0100 @@ -6,5 +6,5 @@ IRQether = IRQgic + 29, }; -#define PCIWINDOW 0 +#define PCIWINDOW soc.pcidmawin #define PCIWADDR(va) (PADDR(va)+PCIWINDOW) diff -r 5c327eddc496 sys/src/9/bcm64/pcibcm.c --- a/sys/src/9/bcm64/pcibcm.c Sat Jan 23 20:36:09 2021 -0800 +++ b/sys/src/9/bcm64/pcibcm.c Fri Jan 29 15:43:55 2021 +0100 @@ -244,6 +244,16 @@ pcibcmlink(void) { int log2dmasize = 30; // 1GB + char *s; + + if((s = getconf("*pciwin")) != nil){ + print("*pciwin: %s\n", s); + soc.pciwin = (uintptr)strtoll(s, nil, 16); + } + if((s = getconf("*pcidmawin")) != nil){ + print("*pcidmawin: %s\n", s); + soc.pcidmawin = (uintptr)strtoll(s, nil, 16); + } regs[RGR1_SW_INIT_1] |= 3; delay(200); @@ -266,8 +276,8 @@ // SCB_ACCESS_EN, CFG_READ_UR_MODE, MAX_BURST_SIZE_128, SCB0SIZE regs[MISC_MISC_CTRL] = 1<<12 | 1<<13 | 0<<20 | (log2dmasize-15)<<27; - regs[MISC_RC_BAR2_CONFIG_LO] = (log2dmasize-15); - regs[MISC_RC_BAR2_CONFIG_HI] = 0; + regs[MISC_RC_BAR2_CONFIG_LO] = ((u32int)soc.pcidmawin & ~0x1F) | (log2dmasize-15); + regs[MISC_RC_BAR2_CONFIG_HI] = soc.pcidmawin >> 32; regs[MISC_RC_BAR1_CONFIG_LO] = 0; regs[MISC_RC_BAR3_CONFIG_LO] = 0; -- cinap