From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 8878 invoked from network); 20 Jan 2021 22:40:36 -0000 Received: from 1ess.inri.net (216.126.196.35) by inbox.vuxu.org with ESMTPUTF8; 20 Jan 2021 22:40:36 -0000 Received: from MTA-08-4.privateemail.com ([198.54.122.58]) by 1ess; Wed Jan 20 17:11:48 -0500 2021 Received: from MTA-08.privateemail.com (localhost [127.0.0.1]) by MTA-08.privateemail.com (Postfix) with ESMTP id DB95660075 for <9front@9front.org>; Wed, 20 Jan 2021 17:11:40 -0500 (EST) Received: from localhost (unknown [10.20.151.249]) by MTA-08.privateemail.com (Postfix) with ESMTPA id DF95D60048 for <9front@9front.org>; Wed, 20 Jan 2021 22:11:39 +0000 (UTC) Date: Wed, 20 Jan 2021 14:11:30 -0800 From: Anthony Martin To: 9front@9front.org Message-ID: References: <6AE51FD76D949F3DCD2772A03858F36C@eigenstate.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Virus-Scanned: ClamAV using ClamSMTP List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: decentralized encrypted CMS realtime-java persistence manager Subject: Re: [9front] Weird >>= operator behaviour in 5c/5l Reply-To: 9front@9front.org Precedence: bulk ori@eigenstate.org once said: > > Only lightly tested, not sure if I have any > > edge cases. > > > I like this version more. > > diff -r 01125acb5565 sys/src/cmd/5l/asm.c > --- a/sys/src/cmd/5l/asm.c Tue Jan 19 19:56:38 2021 -0800 > +++ b/sys/src/cmd/5l/asm.c Tue Jan 19 22:12:05 2021 -0800 > @@ -789,6 +789,12 @@ > r = p->reg; > if(r == NREG) > r = p->to.reg; > + /* > + * R>>32 is encoded as R>>0, so flip to the > + * equivalent R<<0. > + */ > + if(instoffset == 0) > + o1 &= ~(1<<5); > o1 |= r; > o1 |= (instoffset&31) << 7; > o1 |= p->to.reg << 12; > This will affect any assembler source that uses ROR $0, R1, R2 to get at the special RRX arm instruction alias for a rotate right by one bit with extension. That instruction would become SRA $0, R1, R2 for a arithmetic shift right by 32 bits. It's probably not used anywhere but I wanted to make sure you knew about it. For reference, here's my understanding of the possible shift values on arm: a i stype imm5 SLL LSL 00 0..31 SRL LSR 01 1..32 mod 32 SRA ASR 10 1..32 mod 32 ROR ROR 11 1..31 ROR RRX 11 0 Hope that helps. Cheers, Anthony