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Subject:  Re: [9front] strange behaviour of igfx and vesa
Date: Sat, 25 Jun 2016 10:50:08 +0900
From: kokamoto@hera.eonet.ne.jp
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I'm still experimenting this, but no success.

When I posted last mail, and pointed supposed to do some large
rewriting neccessary, which was thought less.

At that time, I was thinking to change in init() function for 29a2 chip.
Now I fugured it was wrong, and am now adding some code in load()
function.

Now experimenting codes are(in load() function):
	/* program vga plane */
	loadreg(igfx, igfx->vgacntrl);

	/* program ports */
/* from here====K.Okamoto====*/
	if(igfx->pci->did == 0x29a2){		/* K.Okamoto */
		wr(igfx, igfx->adpa.a, 1<<31);		/* enable adpa */
		wr(igfx, igfx->adpa.a, 3<<10);		/* off disable hsync/vsync */
		wr(igfx, igfx->adpa.a, 1<<15);		/* use 4,3 bits for hsync/vsync */
//		wr(igfx, 0x070024, 1<<9);
//		while((rr(igfx, 0x070024) & 1<<9) == 0)
//			continue;
//		wr(igfx, 0x070024, 1<<1);
//		wr(igfx, 0x070024, 1<<9);
		wr(igfx, 0x070024, 0x207);
		while((rr(igfx, 0x070024) & 0x207) == 0)
			continue;
		wr(igfx, igfx->adpa.a, 1<<15);		/* use VGA bits for hsync/vsync */
		wr(igfx, igfx->adpa.a, ~(3<<10));		/* adpa hsync/vsynx on */
	}
/* ======to here K.Okamoto======*/
	loadreg(igfx, igfx->adpa);
	igfx->adpa.v &= ~(3<<10);	/* Monitor DPMS: on */

Results are not successfull, however, I suppose I'm now on right truck.
If you have some comments on this, please do it.

Kenji