From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from duke.felloff.net ([216.126.196.34]) by ur; Sat Jul 9 08:48:44 EDT 2016 Message-ID: Date: Sat, 9 Jul 2016 14:48:37 +0200 From: cinap_lenrek@felloff.net To: 9front@9front.org Subject: Re: [9front] core-i3 and vesa mode In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: self-healing responsive shader-based SSL enhancement-aware table yes. it lives outside, but it is accessed from the pci bar! so when the cpu does a store at physical address 0xe0001000, the address is checked against all the pci bars. in our case this is the graphics card so a write is send over pci bus to the graphics card. the graphics card then sees a write to 0x1000 (in its logical address space), then looks up the page in the gtt (second gtt entry) which translates to 0xdba01000. -- cinap