From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mta01.eonet.ne.jp ([203.140.81.21]) by ur; Fri Aug 5 19:58:19 EDT 2016 Received: from titan.jitaku.localdomain (101-141-38-118f1.osk3.eonet.ne.jp [101.141.38.118]) by mailmsa12.mozu.eo.k-opti.ad.jp with ESMTP id u75NwDWJ007615 for <9front@9front.org>; Sat, 6 Aug 2016 08:58:13 +0900 To: 9front@9front.org Subject: Re: [9front] core-i5(TypeSNB) and vesa mode Date: Sat, 6 Aug 2016 08:58:12 +0900 From: kokamoto@hera.eonet.ne.jp Message-ID: In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: injection event I don't get success for 1680x1050x32, though I tried many things. Then, I'm testing DP->hdmi connector case. > Do you get edid from > displayport aux channel? No, I don't. I put a debug line in init() like: case PortDPA: case PortDPB: case PortDPC: case PortDPD: r = &igfx->dp[port - PortDPA].ctl; if(r->a == 0) goto Badport; /* port enable */ print("Passing case PortDP\n"); r->v |= 1<<31; /* port width selection: x1 Mode */ r->v &= ~(7<<19); Nothing printed. I tired display=3~6 in /cfg/pxe/xxxxxx. I changed the sources from your updated one to: 1) in init() /* disable all pipes and ports */ igfx->ppcontrol.v &= 0xFFFF; igfx->ppcontrol.v &= ~5; igfx->lvds.v &= ~(1<<31); igfx->adpa.v &= ~(1<<31); /* from here */ if(igfx->type == TypeSNB){ /* K.Okamoto */ csr(igfx, 0xC6200, 3<<11, 2); /* pch ref souce & ssc enable */ sleep(5); csr(igfx, 0xC6200, 1<<0, 1); /* ssc1 enable */ sleep(5); } /* to here */ if(igfx->type == TypeG45) igfx->adpa.v |= (3<<10); /* Monitor DPMS: off */ for(x=0; xdp); x++) 2) in enablepipe() int i; Pipe *p; p = &igfx->pipe[x]; if((p->conf.v & (1<<31)) == 0) return; /* pipe is disabled, done */ if(p->fdi->rxctl.a != 0){ p->fdi->rxctl.v &= ~(1<<31); p->fdi->rxctl.v &= ~(1<<4); /* rawclk */ p->fdi->rxctl.v |= (1<<13); /* enable pll */ loadreg(igfx, p->fdi->rxctl); sleep(5); p->fdi->rxctl.v |= (1<<4); /* pcdclk */ loadreg(igfx, p->fdi->rxctl); sleep(5); /* from here */ p->fdi->txctl.v &= ~(7<<8 | 1); /* clear auto training bits */ if(igfx->type != TypeSNB) p->fdi->txctl.v &= ~(1<<31); /* disable */ p->fdi->txctl.v |= (1<<14); /* enable FDI pll */ loadreg(igfx, p->fdi->txctl); sleep(5); /* to here */ } /* image size (vga needs to be off) */ loadreg(igfx, p->src); Kenji PS. By the way, I haven't get edid data all from the beginning, which means I didn't change the source anything.