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Received: from duke.felloff.net ([216.126.196.34]) by ur; Wed Jul 27 17:41:50 EDT 2016
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Date: Wed, 27 Jul 2016 23:41:42 +0200
From: cinap_lenrek@felloff.net
To: 9front@9front.org
Subject: Re: [9front] core-i5(TypeSNB) and vesa mode
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X-Bullshit: information high-performance injection-oriented controller 

		if(igfx->pci->did == 0x0152)	/* 2nd/3rd Gen Core - Core-i3 */
			igfx->cdclk = 350;	/* MHz */
		else
			igfx->cdclk = 400;	/* MHz */

where did you got the 350 MHz cdclk value from? the documentation from
https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part3.pdf
states: "On Ivybridge the core display clock frequency is 400 MHz".

also, where did you got the 667 MHz value for G45 from?

		if(igfx->pci->did == 0x29a2)		/*  82P965/G965 HECI desktop  */
			igfx->cdclk = 667;	/* MHz */
		else
			igfx->cdclk = 200;	/* MHz */

--
cinap