From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (from majordomo@localhost) by pauillac.inria.fr (8.7.6/8.7.3) id OAA06592; Mon, 19 Aug 2002 14:56:08 +0200 (MET DST) X-Authentication-Warning: pauillac.inria.fr: majordomo set sender to owner-caml-list@pauillac.inria.fr using -f Received: from concorde.inria.fr (concorde.inria.fr [192.93.2.39]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id OAA06713 for ; Mon, 19 Aug 2002 14:56:07 +0200 (MET DST) Received: from pauillac.inria.fr (pauillac.inria.fr [128.93.11.35]) by concorde.inria.fr (8.11.1/8.11.1) with ESMTP id g7JCu5T09961; Mon, 19 Aug 2002 14:56:05 +0200 (MET DST) Received: (from xleroy@localhost) by pauillac.inria.fr (8.7.6/8.7.3) id OAA06676; Mon, 19 Aug 2002 14:56:05 +0200 (MET DST) Date: Mon, 19 Aug 2002 14:56:05 +0200 From: Xavier Leroy To: William Chesters Cc: caml-list@inria.fr Subject: Re: float array alignment; was Re: [Caml-list] Bigarray access speed Message-ID: <20020819145605.A6276@pauillac.inria.fr> References: <20020815225004.GA5959@gromit.it.su.se> <15708.56593.451087.185083@beertje.william.bogus> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Mailer: Mutt 1.0i In-Reply-To: <15708.56593.451087.185083@beertje.william.bogus>; from williamc@paneris.org on Fri, Aug 16, 2002 at 12:08:01PM +0100 Sender: owner-caml-list@pauillac.inria.fr Precedence: bulk malc writes: > To get maximal speed of the inner loops data needs to be naturally > aligned. OCaml does nothing to enforce it for non-big arrays. Bigarrays on > the other hand are mmaped(4k on IA32) and you get perfectly aligned data > for free. I was thinking that maybe Array can be extended with > make[create]_aligned, for speed/space tradeoff. As William Chester said, allocating 8-aligned arrays isn't really hard, but keeping them 8-aligned across copying collection, compaction, and structured I/O is quite a pain. My experiments indicate that the lack of alignment on float arrays (or more precisely the fact that they are 4-aligned instead of 8-aligned) has negligible impact on performance for the IA32 (Pentium) and PowerPC processors, but non-negligible for SPARC and MIPS. And of course on a 64-bit architecture the problem goes away because everything in the Caml heap is then 8-aligned. Since I expect IA32 and PowerPC to remain dominant until we massively switch to 64-bit processors, there's no urgent need to do something about float array alignment. - Xavier Leroy ------------------- To unsubscribe, mail caml-list-request@inria.fr Archives: http://caml.inria.fr Bug reports: http://caml.inria.fr/bin/caml-bugs FAQ: http://caml.inria.fr/FAQ/ Beginner's list: http://groups.yahoo.com/group/ocaml_beginners