From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Original-To: caml-list@yquem.inria.fr Delivered-To: caml-list@yquem.inria.fr Received: from nez-perce.inria.fr (nez-perce.inria.fr [192.93.2.78]) by yquem.inria.fr (Postfix) with ESMTP id D7CD8BB81 for ; Wed, 22 Mar 2006 10:20:11 +0100 (CET) Received: from kvi.nl (KVIS12.KVI.nl [129.125.27.62]) by nez-perce.inria.fr (8.13.0/8.13.0) with ESMTP id k2M9KB3s015518 (version=TLSv1/SSLv3 cipher=DES-CBC3-SHA bits=168 verify=NO) for ; Wed, 22 Mar 2006 10:20:11 +0100 Received: from KVIR52.KVI.nl ([129.125.37.116] verified) by kvi.nl (CommuniGate Pro SMTP 4.3.9) with ESMTP id 4090294 for caml-list@yquem.inria.fr; Wed, 22 Mar 2006 10:20:10 +0100 Received: from kvis12.kvi.nl by KVIR52.KVI.nl (AvMailGate-2.0.4-7) id 24705-78DFD475; Wed, 22 Mar 2006 10:20:10 +0100 Received: by kvis12.kvi.nl (Postfix, from userid 0) id 8EBB0C40BB; Wed, 22 Mar 2006 10:20:10 +0100 (CET) Received: from [129.125.15.152] (HELO kvip88) by kvi.nl (CommuniGate Pro SMTP 4.3.9) with ESMTPS id 4090293 for caml-list@yquem.inria.fr; Wed, 22 Mar 2006 10:20:10 +0100 From: "Alexander S. Usov" Organization: KVI To: caml-list@yquem.inria.fr Subject: Re: [Caml-list] Severe loss of performance due to new signal handling (fwd) Date: Wed, 22 Mar 2006 10:20:09 +0100 User-Agent: KMail/1.9.1 References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="koi8-r" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200603221020.09917.A.S.Usov@kvi.nl> X-AntiVirus: checked by AntiVir MailGate (version: 2.0.4-7; AVE: 6.34.0.14; VDF: 6.34.0.82; host: kvi.nl) X-Miltered: at nez-perce with ID 442116CB.000 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Spam: no; 0.00; off-list:01 parallelism:01 rdtsc:01 rdtsc:01 model:01 2006:98 2006:98 wrote:01 wrote:01 caml-list:01 caml-list:01 grep:01 hmm:02 alexander:03 alexander:03 X-Spam-Checker-Version: SpamAssassin 3.0.3 (2005-04-27) on yquem.inria.fr X-Spam-Level: X-Spam-Status: No, score=0.1 required=5.0 tests=FORGED_RCVD_HELO autolearn=disabled version=3.0.3 On Wednesday 22 March 2006 00:53, Brian Hurt wrote: > Opps- didn't intend this message to be off-list. > > ---------- Forwarded message ---------- > Date: Tue, 21 Mar 2006 16:32:51 -0600 (CST) > From: Brian Hurt > To: Robert Roessler > Subject: Re: [Caml-list] Severe loss of performance due to new signal > handling > > On Tue, 21 Mar 2006, Robert Roessler wrote: > > Well, I *thought* there was a marked absence of "bit-level parallelism" > > in the signal-handling... ;) > > > > So the "expense" of individual atomic operations is not really what is at > > the heart of this performance problem... > > Hmm. Maybe not. I'm measuring a 4 clock cycle cost for a xchgl, both with > and without a lock on my Athlon XP 1.8GHz. See attached code. Naturally, > this is a uniprocessor machine and the memory location is in L1 cache (or > will be soon), and no contention, so this is definately best case. 4 > clocks is about rights for a read and a write to L1 cache (each L1 cache > access taking 2 clocks). $ ./a.out Minimum time for a rdtsc instruction (in clocks): 88 Minimum time for a read_and_clear() + rdtsc (in clocks): 248 $ grep 'model name' /proc/cpu model name : Intel(R) Pentium(R) 4 CPU 2.00GHz -- Best regards, Alexander.