Re: [Caml-list] Array 4 MB size limit

[Oliver Bandel <oliver@first.in-berlin.de>]

On Sun, May 21, 2006 at 11:24:34AM +1000, skaller wrote:
> On Sat, 2006-05-20 at 23:42 +0200, Oliver Bandel wrote:
> > On Sat, May 20, 2006 at 08:12:22PM +1000, skaller wrote:
> 
> > Two dual core G5:
> > 
> >   http://www.apple.com/powermac/
> 
> We're looking at how N will increase in N-core CPU chips. 
> 
> There are plenty of boards that support
> multiple CPUs (you can get a 8x Opteron board, that's 16 cores,
> and not really that expensive -- the CPUs are though :).
> 
> 'In theory' CISC should die, RISC should support higher N
> on the same wafer.
[...]

Please do not forget that the G5 is a 64-Bit processor!

http://www.apple.com/g5processor/


So if you have a 2 x DualCore G5 then you have
four 64-Bit Cores on your computer.

Even when the Processors then switch to 64 Bits,
the next problem would be to have RAMs available
that are big enough to use that.


Ciao,
   Oliver