From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Original-To: caml-list@yquem.inria.fr Delivered-To: caml-list@yquem.inria.fr Received: from nez-perce.inria.fr (nez-perce.inria.fr [192.93.2.78]) by yquem.inria.fr (Postfix) with ESMTP id 5210BBBAF for ; Sun, 21 May 2006 16:10:27 +0200 (CEST) Received: from pauillac.inria.fr (pauillac.inria.fr [128.93.11.35]) by nez-perce.inria.fr (8.13.0/8.13.0) with ESMTP id k4LEAQGx026918 for ; Sun, 21 May 2006 16:10:26 +0200 Received: from nez-perce.inria.fr (nez-perce.inria.fr [192.93.2.78]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id QAA25566 for ; Sun, 21 May 2006 16:10:26 +0200 (MET DST) Received: from einhorn.in-berlin.de (einhorn.in-berlin.de [192.109.42.8]) by nez-perce.inria.fr (8.13.0/8.13.0) with ESMTP id k4LEAPcs026913 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL) for ; Sun, 21 May 2006 16:10:25 +0200 X-Envelope-From: oliver@first.in-berlin.de X-Envelope-To: Received: from first.in-berlin.de (e178011229.adsl.alicedsl.de [85.178.11.229]) (authenticated bits=0) by einhorn.in-berlin.de (8.13.6/8.13.6/Debian-1) with ESMTP id k4LEAMLa005494 for ; Sun, 21 May 2006 16:10:22 +0200 Received: by first.in-berlin.de (Postfix, from userid 501) id AB47428C1BD; Sun, 21 May 2006 16:10:31 +0200 (CEST) Date: Sun, 21 May 2006 16:10:31 +0200 From: Oliver Bandel To: caml-list@inria.fr Subject: Re: [Caml-list] Array 4 MB size limit Message-ID: <20060521141030.GA1771@first.in-berlin.de> References: <446986DF.1070308@inria.fr> <446D5E4A.8060005@akalin.cx> <20060519162844.GA32550@osiris.uid0.sk> <20060520090826.GB32550@osiris.uid0.sk> <1148119942.8693.18.camel@rosella.wigram> <20060520214208.GD2670@first.in-berlin.de> <1148174674.12058.36.camel@rosella.wigram> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1148174674.12058.36.camel@rosella.wigram> User-Agent: Mutt/1.5.6i X-Scanned-By: MIMEDefang_at_IN-Berlin_e.V. on 192.109.42.8 X-Miltered: at nez-perce with ID 447074D2.000 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Miltered: at nez-perce with ID 447074D1.000 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Spam: no; 0.00; bandel:01 in-berlin:01 bandel:01 2006:98 2006:98 20,:98 wrote:01 wrote:01 caml-list:01 oliver:01 oliver:01 bits:04 processors:04 size:95 problem:05 X-Spam-Checker-Version: SpamAssassin 3.0.3 (2005-04-27) on yquem.inria.fr X-Spam-Level: X-Spam-Status: No, score=0.1 required=5.0 tests=FORGED_RCVD_HELO autolearn=disabled version=3.0.3 On Sun, May 21, 2006 at 11:24:34AM +1000, skaller wrote: > On Sat, 2006-05-20 at 23:42 +0200, Oliver Bandel wrote: > > On Sat, May 20, 2006 at 08:12:22PM +1000, skaller wrote: > > > Two dual core G5: > > > > http://www.apple.com/powermac/ > > We're looking at how N will increase in N-core CPU chips. > > There are plenty of boards that support > multiple CPUs (you can get a 8x Opteron board, that's 16 cores, > and not really that expensive -- the CPUs are though :). > > 'In theory' CISC should die, RISC should support higher N > on the same wafer. [...] Please do not forget that the G5 is a 64-Bit processor! http://www.apple.com/g5processor/ So if you have a 2 x DualCore G5 then you have four 64-Bit Cores on your computer. Even when the Processors then switch to 64 Bits, the next problem would be to have RAMs available that are big enough to use that. Ciao, Oliver