From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on yquem.inria.fr X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=disabled version=3.1.3 X-Original-To: caml-list@yquem.inria.fr Delivered-To: caml-list@yquem.inria.fr Received: from discorde.inria.fr (discorde.inria.fr [192.93.2.38]) by yquem.inria.fr (Postfix) with ESMTP id DD799BC0A for ; Tue, 13 Mar 2007 16:55:06 +0100 (CET) Received: from relay.felk.cvut.cz (relay.felk.cvut.cz [147.32.80.7]) by discorde.inria.fr (8.13.6/8.13.6) with ESMTP id l2DFt6VD017226 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 13 Mar 2007 16:55:06 +0100 Received: from dsd07.felk.cvut.cz (dsd07.felk.cvut.cz [147.32.80.75]) by relay.felk.cvut.cz (8.13.8/8.13.8) with ESMTP id l2DFsmdh007143 for ; Tue, 13 Mar 2007 16:54:48 +0100 (CET) (envelope-from kubatova@dsd07.felk.cvut.cz) Received: from dsd07.felk.cvut.cz (dsd07.felk.cvut.cz [147.32.80.75]) by dsd07.felk.cvut.cz (8.13.8/8.13.8) with ESMTP id l2DFsl6L050102 for ; Tue, 13 Mar 2007 16:54:47 +0100 (CET) (envelope-from kubatova@dsd07.felk.cvut.cz) Received: (from kubatova@localhost) by dsd07.felk.cvut.cz (8.13.8/8.13.8/Submit) id l2DFslro050100 for caml-list@inria.fr; Tue, 13 Mar 2007 16:54:47 +0100 (CET) (envelope-from kubatova) Date: Tue, 13 Mar 2007 16:54:47 +0100 (CET) From: Hana Kubatova Message-Id: <200703131554.l2DFslro050100@dsd07.felk.cvut.cz> To: caml-list@inria.fr Subject: DSD'2007 submission deadline extended to March 25 MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-2 X-FELK-MailScanner-Information: X-FELK-MailScanner: Found to be clean X-FELK-MailScanner-SpamCheck: not spam, SpamAssassin (cached, score=-1.899, required 5, ALL_TRUSTED -1.80, BAYES_00 -2.60, FELK_HEALTH_SUBJ 1.50, RAZOR2_CHECK 1.00) X-FELK-MailScanner-From: kubatova@dsd07.felk.cvut.cz X-Miltered: at discorde with ID 45F6C95A.002 by Joe's j-chkmail (http://j-chkmail . ensmp . fr)! X-Spam: no; 0.00; cfp:01 cfp:01 prototyping:01 reuse:01 arrays:01 parametric:01 prototyping:01 synthesis:01 synthesis:01 nano:01 wearable:01 node:01 trade-offs:01 low-power:01 aggregation:01 Dear Colleague, due to many requests from the prospective authors the Submission Deadline for DSD'2007 has been prolonged once more. The Important Dates are now as follows: Submission of papers: March 25, 2007 Notification of acceptance: May 3, 2007 Camera-ready papers: June 9, 2007 DSD'2007 Conference: August 27 - August 31, 2007 Please follow the links to see the DSD'2007 Call for Papers and Call for Papers for each Special Session. A brief info with areas of interest follows. DSD'2007 conference Call for Papers: http://dsd07.felk.cvut.cz/DSD2007.pdf SS1: Resource Aware Sensor Network Systems http://www-md.e-technik.uni-rostock.de/ma/hm13/dsd07/cfp_SNS_DSD2007.pdf SS2: Advanced issues of Networks-on-Chip http://www-md.e-technik.uni-rostock.de/ma/cc14/dsd07/cfp_NOC_DSD2007.pdf SS3: Dependability and Testing of Digital Systems http://dsd07.felk.cvut.cz/test/cfp.pdf ************************************************************************** Call For Papers DSD 2007 10th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN Architectures, Methods and Tools August 27 - 31, 2007, Lübeck in Germany conference web pages: http://dsd07.felk.cvut.cz http://www.dsdconf.org/ Important dates: *************** Submission of papers: March 25, 2007 Notification of acceptance: May 3, 2007 Deadline for final version: June 9, 2007 Deadline for registration: June 9, 2007 The main areas of interest are the following: T1: Systems-on-a-chip/in-a-package: - generic system platforms and platform-based design - network on chip - multi-processors - system on re-configurable chip - system FPGAs and structured ASICs - rapid prototyping - asynchronous systems - power, energy, timing, predictability and other quality issues - intellectual property, virtual components and design reuse T2: Programmable/re-configurable architectures: - re-configurable system architectures, processor, communication, memory and software architectures with focus on application specific and/or embedded computing, co-processors - processing arrays - programmable fabrics - embedded software - arithmetic, logic and special-operator units T3: System, hardware and embedded software specification, modeling and validation: - design languages - functional, structural and parametric specification and modeling - simulation, emulation, prototyping, and testing at the system, register-transfer, logic and physical levels - co-simulation and co-verification. T4: System, hardware and embedded software synthesis: - system, hardware/software and embedded software synthesis - behavioral, register-transfer, logic and physical circuit synthesis - multi-objective optimization observing power, performance, communication, interconnections, layout, technology, reliability, robustness, security, testability and other issues - (dynamic) management of computational resources, power, energy etc. - design environments for embedded systems. T5: Emerging technologies, system paradigms and design methodologies: - optical, bio, nano and quantum technologies and computing - self-organizing and self-adapting (wireless) systems - wireless sensor networks - ambient intelligence and augmented reality - ubiquitous, wearable and implanted systems - deep sub-micron design issues. T6: Applications of (embedded) digital systems with emphasis on demanding and new applications in fields such as - (wireless) communication and networking - measurement and instrumentation - health-care and medicine - military, space, avionic and automotive systems - security - multi-media, instrumentation and ambient intelligence. The areas of interrest of special section is following: SS1: Resource Aware Sensor Network Systems The special session on "Resource-Aware Sensor Network Systems" addresses concepts, implementations and applications of sensor network systems, as well as, new architectural models and hardware solutions in the sensor network domain. Papers on any of the following and related topics will be considered for the special session: - Sensor node architectures - Sensing, processing, and communicating on a chip - Communication-computation trade-offs - Resource-aware software/hardware co-design - Low-power strategies in hardware design - Energy harvesting strategies - Position determination and synchronization in sensor networks - In-Network processing and aggregation - Fault-tolerant and reliable hardware - Prototypes and applications SS2: Advanced issues of Networks-on-Chip This special session addresses all aspects related to concepts, implementations and applications of networks-on-chip as well as related EDA tools. Nonetheless, its focus is on advanced issues and interdisciplinary topics like system control, design flow, application studies and the outlook on future developments in NOC design. Papers on any of the following and related topics will be considered for the special session: - Future concepts and architectures: Links, Routers, Topology - Reconfiguration and Hardwired NOCs on FPGAs - Programming models, Application mapping, Benchmarking - Operating systems and System control - Reliability, Fault-tolerance, Robustness - Verification and Testability - Design flow and Design space exploration - Prototypes and Application studies. SS3: Dependability and Testing of Digital Systems The special session on "Dependability and Testing of Digital Systems" addresses emerging issues, hot problems, new solution methods and their hardware and software implementations in all fields of digital and mixed-signal system dependability and testing. Its special focus is on the dependability and testing related to the SoC technology and modern embedded applications: - Built-in Self-Test - off-line BIST and on-line BIST - SoC and NoC Dependability and Testing - Robust Circuit and System Design - On-line testing; IDDQ and Current Testing - Defect/Fault Tolerance - Dependability and Reliability - Modeling and Computations - Synthesis for Testability - Diagnosis Embedded Test - Analog, Mixed-Signal and RF Test - Memory and Processor Test. Sincerely, Hana Kubatova DSD'2007 Program Chairman kubatova@dsd07.felk.cvut.cz