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[82.237.71.191]) by smtp.gmail.com with ESMTPSA id s30sm12737418wrc.13.2017.06.30.10.03.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Jun 2017 10:03:22 -0700 (PDT) Sender: Xavier Leroy To: caml-list@inria.fr References: <0ea087b1-7267-eee6-3dd5-55a760d8f4cd@inria.fr> <49E937AA-CACC-4525-9AF2-113AB4B47B69@gmail.com> From: Xavier Leroy Message-ID: <2dc653a6-4b1c-c22a-dfc7-382b2508be03@inria.fr> Date: Fri, 30 Jun 2017 19:03:21 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <49E937AA-CACC-4525-9AF2-113AB4B47B69@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [Caml-list] [IMPORTANT] Intel Skylake / Kaby Lake hardware bug affects OCaml programs On 06/30/2017 06:46 PM, Anton Bachin wrote: > In what I’ve read about the bug, there is no requirement that two virtual cores be running OCaml code (or rather, the malfunctioning instruction sequence). Is that accurate? That's my guess, too, based on Intel's cryptic description of the issue. ("Complex set of micro-architectural conditions", you don't say!) However, the two repro cases I worked with (the one from Ahrefs and the earlier one) were both of the "running several copies of an OCaml program in parallel" kind. - Xavier Leroy