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From: Tom Hawkins <tom@confluent.org>
To: caml-list@yquem.inria.fr
Subject: HDCaml 0.1.0
Date: Fri, 16 Sep 2005 13:38:24 -0500	[thread overview]
Message-ID: <432B1120.9050909@confluent.org> (raw)

I just started a framework for describing hardware structures in OCaml. 
  Given a functional hardware description, HDCaml will produce a Verilog 
netlist for verification and implementation.

HDCaml also has decent PSL support for assertion based verification.

Current Limitations:
   - Synchronous, single clock.
   - No black boxing.
   - Basic regs only.  No memories.
   - Flat netlisting.

Possible Future Directions:
   - Better clock control.
   - Hierarchical netlisting.
   - C, VHDL, NuSMV code generation.
   - Links to HOL Light.

Any recommendations on the API structure or library features would be 
appreciated.

-Tom



HDCaml Download:

   http://www.confluent.org/

API Docs:

   http://www.confluent.org/misc/hdcaml/Hdcaml.html


                 reply	other threads:[~2005-09-16 18:38 UTC|newest]

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