* HDCaml 0.1.0
@ 2005-09-16 18:38 Tom Hawkins
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From: Tom Hawkins @ 2005-09-16 18:38 UTC (permalink / raw)
To: caml-list
I just started a framework for describing hardware structures in OCaml.
Given a functional hardware description, HDCaml will produce a Verilog
netlist for verification and implementation.
HDCaml also has decent PSL support for assertion based verification.
Current Limitations:
- Synchronous, single clock.
- No black boxing.
- Basic regs only. No memories.
- Flat netlisting.
Possible Future Directions:
- Better clock control.
- Hierarchical netlisting.
- C, VHDL, NuSMV code generation.
- Links to HOL Light.
Any recommendations on the API structure or library features would be
appreciated.
-Tom
HDCaml Download:
http://www.confluent.org/
API Docs:
http://www.confluent.org/misc/hdcaml/Hdcaml.html
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2005-09-16 18:38 HDCaml 0.1.0 Tom Hawkins
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