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([2601:240:c600:8bd0:8075:2fd9:1008:24ed]) by smtp.gmail.com with ESMTPSA id m2sm2238026iti.26.2017.06.30.09.46.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Jun 2017 09:46:25 -0700 (PDT) Content-Type: multipart/alternative; boundary="Apple-Mail=_E3C6758C-CA9C-4E98-B069-05B029000067" Mime-Version: 1.0 (Mac OS X Mail 10.3 \(3273\)) From: Anton Bachin In-Reply-To: Date: Fri, 30 Jun 2017 11:46:24 -0500 Cc: Gabriel Scherer , Xavier Leroy , OCaml Mailing List X-Mao-Original-Outgoing-Id: 520533984.820068-255edb049b82e366ff881426350e285a Message-Id: <49E937AA-CACC-4525-9AF2-113AB4B47B69@gmail.com> References: <0ea087b1-7267-eee6-3dd5-55a760d8f4cd@inria.fr> To: Julia Lawall X-Mailer: Apple Mail (2.3273) Subject: Re: [Caml-list] [IMPORTANT] Intel Skylake / Kaby Lake hardware bug affects OCaml programs --Apple-Mail=_E3C6758C-CA9C-4E98-B069-05B029000067 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 In what I=E2=80=99ve read about the bug, there is no requirement that two v= irtual cores be running OCaml code (or rather, the malfunctioning instructi= on sequence). Is that accurate? If so, it shouldn=E2=80=99t matter whether = the OCaml code is parallelized or not. As far as I know, the users reporting in Lwt were not running Lwt or OCaml = in parallel. > El jun. 30, 2017, a las 11:30, Julia Lawall > escribi=C3=B3: >=20 >=20 >=20 > On Fri, 30 Jun 2017, Gabriel Scherer wrote: >=20 >> Here is my list of affected OCaml projects known so far (it seems >> surprisingly less rare than I thought at first): >>=20 >> - an (unnamed) industrial user noticed the issue in Spring 2016, as >> reported by Xavier on the bugtracker: >> https://caml.inria.fr/mantis/view.php?id=3D7452#c17109 >>=20 >> - ahrefs noticed issues in late 2016, as reported by Joris >> Giovannangeli on the bugtracker issue or his longer piece >> https://tech.ahrefs.com/skylake-bug-a-detective-story-ab1ad2beddcd >>=20 >> - Lwt users were also affected (first report from Sebastien Mondet in >> February 2017): >> https://github.com/ocsigen/lwt/issues/315 >>=20 >> - Julia Lawall reported segfaults from a downstream user on the caml-lis= t, >> that seem extreley likely to be related to this issue (they >> disappear with hyperthreading disabled) >> https://sympa.inria.fr/sympa/arc/caml-list/2017-06/msg00115.html >>=20 >> At this point it seems reasonable to assume that any >> computation-intensive OCaml program that is run in parallel may be >> affected. >=20 > The Coccinelle code is compiled with Parmap, but I don't think that Parmap > is invoked in the failing execution. I could check on this. >=20 > julia >=20 >=20 >>=20 >> On Fri, Jun 30, 2017 at 10:15 AM, Xavier Leroy > wrote: >>> Clarification: >>>=20 >>>> Possible fixes include: >>>>=20 >>>> - Apply the microcode update recently released by Intel [...] >>>=20 >>> Contradicting what I wrote before, microcode updates are available both= for Skylake and for Kaby Lake processors. It's only how to apply those up= dates that differs slightly between Skylake and Kaby Lake. Again, see the e= xcellent instructions at >>> https://lists.debian.org/debian-devel/2017/06/msg00308.html >>>=20 >>> Sorry for the confusion. >>>=20 >>> - Xavier Leroy >>>=20 >>> -- >>> Caml-list mailing list. Subscription management and archives: >>> https://sympa.inria.fr/sympa/arc/caml-list >>> Beginner's list: http://groups.yahoo.com/group/ocaml_beginners >>> Bug reports: http://caml.inria.fr/bin/caml-bugs >>=20 >> -- >> Caml-list mailing list. Subscription management and archives: >> https://sympa.inria.fr/sympa/arc/caml-list >> Beginner's list: http://groups.yahoo.com/group/ocaml_beginners >> Bug reports: http://caml.inria.fr/bin/caml-bugs >>=20 >=20 > --=20 > Caml-list mailing list. Subscription management and archives: > https://sympa.inria.fr/sympa/arc/caml-list > Beginner's list: http://groups.yahoo.com/group/ocaml_beginners > Bug reports: http://caml.inria.fr/bin/caml-bugs --Apple-Mail=_E3C6758C-CA9C-4E98-B069-05B029000067 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8
In wh= at I=E2=80=99ve read about the bug, there is no requirement that two virtua= l cores be running OCaml code (or rather, the malfunctioning instruction se= quence). Is that accurate? If so, it shouldn=E2=80=99t matter whether the O= Caml code is parallelized or not.

As far as I know, the users reporting in Lwt were not runn= ing Lwt or OCaml in parallel.

El jun. 30, 2017, a las 11:30, Julia Lawal= l <julia.lawall@lip6.= fr> escribi=C3=B3:



<= span style=3D"font-family: Menlo-Regular; font-size: 13px; font-style: norm= al; font-variant-caps: normal; font-weight: normal; letter-spacing: normal;= text-align: start; text-indent: 0px; text-transform: none; white-space: no= rmal; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; displ= ay: inline !important;" class=3D"">On Fri, 30 Jun 2017, Gabriel Scherer wro= te:

Her= e is my list of affected OCaml projects known so far (it seems
surprisingly less rare than I thought at first):

- an (unnamed) industrial user noticed the issue in Spring 2016, asreported by Xavier on the bugtracker:
 h= ttps://caml.inria.fr/mantis/view.php?id=3D7452#c17109
- ahrefs noticed issues in late 2016, as reported by Joris
Giovannangeli on the bugtracker issue or his longer piece
 https://tech.ahrefs.com/skylake-bug-a-detective= -story-ab1ad2beddcd

- Lwt users were also = affected (first report from Sebastien Mondet in
February 2017= ):
 https://github.com/ocsigen/lwt/issues/315
- Julia Lawall reported segfaults from a downstream user on th= e caml-list,
 that seem extreley likely to be related to= this issue (they
disappear with hyperthreading disabled)
 https://sympa.inria.fr/sympa/arc/caml-list/20= 17-06/msg00115.html

At this point it seems= reasonable to assume that any
computation-intensive OCaml pr= ogram that is run in parallel may be
affected.
=

The Coccinelle code is compiled w= ith Parmap, but I don't think that Parmap
is invoked in the failing execution.  I could check on this.<= br style=3D"font-family: Menlo-Regular; font-size: 13px; font-style: normal= ; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; t= ext-align: start; text-indent: 0px; text-transform: none; white-space: norm= al; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=3D"">
julia



On Fri, Jun 30, 2017 at 10:15 AM, Xavier Leroy = <xavier.leroy@inria.= fr> wrote:
Clarif= ication:

= Possible fixes include:

- Apply the microcode = update recently released by Intel [...]

Contradicting what I wrote before, microcode updates are available b= oth for Skylake and for Kaby Lake processors.  It's only how to apply = those updates that differs slightly between Skylake and Kaby Lake. Again, s= ee the excellent instructions at
https://lists.debian= .org/debian-devel/2017/06/msg00308.html

So= rry for the confusion.

- Xavier Leroy

--
Caml-list mailing list.  Subscri= ption management and archives:
https://sympa.inria.fr/sympa/arc/caml-l= ist
Beginner's list: http://groups.yahoo.com/group/ocaml_= beginners
Bug reports: http://caml.inria.fr/bin/caml-bugs

--
Caml-list mailing l= ist.  Subscription management and archives:
https://sympa.inria.f= r/sympa/arc/caml-list
Beginner's list: http://groups.yahoo.com/= group/ocaml_beginners
Bug reports: http://caml.inria.fr/bin/caml-bugs<= br class=3D"">

-- 
Caml-list mailing list.  Subscription management and archive= s:
https://sympa.inria.fr/sympa/arc/caml-list<= /a>
Beginner's list: http://grou= ps.yahoo.com/group/ocaml_beginners
Bug repo= rts: http://caml.inria.fr/bin/caml-bugs
= --Apple-Mail=_E3C6758C-CA9C-4E98-B069-05B029000067--