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78cf2d589d092e0b Message-ID: <7c32c8640910052242n1b867390u2df6fcc109e3e25d@mail.gmail.com> Subject: HLDVT 2009 Call for Participation: Early Registration Deadline From: Shireesh Verma To: acl2@cs.utexas.edu, acl@cs.columbia.edu, agents@cs.umbc.edu, aiia@di.unito.it, asci@twi.tudelft.nl, apng-all@apng.org, appsem@disi.unige.it, appsem-discussion@harlequin.co.ukans, bcs-hci-request@jiscmail.ac.uk, benelog@cs.kuleuven.ac.be, bista@di.unipi.it, calligramme@loria.fr, caml-list@inria.fr, categories@mta.ca, clean-list@cs.kun.nl, clp@comp.nus.edu.sg, clpr-users@comp.nus.edu.sg, cofi-reactive@brics.dk, collinsp@scot.ac.uk, comlab@comlab.ox.ac.uk, complog@cs.nmsu.edu, comprox@doc.ic.ac.uk, compulognet-parimp@dia.fi.upm.es, compunode@compulog.org, compunode@ecrc.de, concurrency@cwi.nl, coq-club@pauillac.inria.fr, csp@carlit.toulouse.inra.fr, cyber-security@stevens-tech.edu, DAI-List@ece.sc.edu, daimi-employees@brics.dk, dbworld@cs.wisc.edu, DMANET@zpr.uni-koeln.de, ea@ira.uka.de, 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agroce@cs.cmu.edu, ledonne@cs.cmu.edu, sccblom@cwi.nl, bertl@cwi.nl, abhik@comp.nus.edu.sg, moore@cs.utexas.edu, scols@ulb.ac.be, rene@ele.kth.se, alur@central.cis.upenn.edu, vivek@csa.iisc.ernet.in, nguyen@cri.ensmp.fr, kareny@galileo.co.il, lawford@mcmaster.ca, sokolsky@saul.cis.upenn.edu, tac@cs.rice.edu, nakagawa@sra.co.jp, ajh@cs.ubc.ca, levin@research.bell-labs.com, yoneda@cs.titech.ac.jp, orna@cs.technion.ac.il, ask@cs.tut.fi, naumann@cs.stevens-tech.edu, myers@ee.elen.utah.edu, elena@ele.kth.se, gopi@csa.iisc.ernet.in, shengru@cs.uno.edu, stoller@cs.sunysb.edu, fabio@colorado.edu, tamirh@cs.technion.ac.il, David.Sinclair@compapp.dcu.ie, namla@cs.utexas.edu, schmidt@cis.ksu.edu, stephane@umich.edu, fmavaddat@uwaterloo.ca, yrodeh@wisdom.weizmann.ac.il, dawnsong@cs.berkeley.edu, yonezaki@cs.titech.ac.jp, Xavier.Leroy@inria.fr, sharonzu@cs.huji.ac.ilf, wpr@informatik.uni-kiel.de, jcottin@is.s.u-tokyo.ac.jp, piazza@dimi.uniud.it, Keijo.Heljanko@hut.fi, kravi@cadence.com, jrb@cadence.com, brayton@eecs.berkeley.edu, ms@informatik.uni-kiel.de, ashar@nec-lab.com, jhkim@formal.korea.ac.kr, michael.moeller@informatik.uni-oldenburg.de, hoenicke@informatik.uni-oldenburg.de, cabodi@polito.it, reps@cs.wisc.edu, mcb@informatik.uni-mannheim.de, Christine.Paulin@lri.fr, pbj@dcs.ed.ac.uk, Olivier.Bournez@loria.fr, ching-tsun.chou@intel.com, tinkler2002@yahoo.com, khurshid@lcs.mit.edu, jhala@cs.berkeley.edu, mky@informatik.uni-kiel.de, kba@informatik.uni-kiel.de, fantechi@dsi.unifi.it, M.C.W.Geilen@tue.nl, helke@cs.tu-berlin.de, kgl@cs.auc.dk Content-Type: multipart/alternative; boundary=00c09f8e5d614a865d04753db39a X-Spam: no; 0.00; synthesis:01 high-level:01 synthesis:01 high-level:01 2009:98 2009:98 discounted:98 discounted:98 graphics:02 graphics:02 W11:96 informal:04 informal:04 debug:05 debug:05 --00c09f8e5d614a865d04753db39a Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable IEEE International High Level DesignValidation and Test Workshop 2009 *November 4-6, 2009* *Grand Hyatt, San Francisco (Union Square)* Register at http://www.hldvt.com/09/registration.html before *October 7**th= * to receive discounted registration rates. Book your hotel room in the heart of San Francisco at a discounted rate of $140. For the past 13 years, IEEE International High Level Design Validation and Test Workshop has been a platform for addressing emerging challenges in verification and test methodologies for ICs and systems. The workshop is an informal forum where EDA tool developers, academics, and industrial practitioners get together to discuss contemporary issues in verification, debug, synthesis, and test. *This year's program will feature=85.* =B7 Keynote Address by *Sunil R. Shenoy* - Vice President, Intel Architecture Group, and General Manager, Microprocessor and Graphics Development - Intel Corporation =B7 Seventeen Regular Papers =B7 Panel: *SystemC Why: To Design or to Verify? What experts say?* =B7 Special Session: *Innovative Industrial Practices* =B7 Three Invited Sessions: =B7 *RTL Validation and Debug*** =B7 *High-Level Modeling and Validation*** =B7 *Post-Silicon Validation and Debug* *Helpful Links:* Advance Program: http://www.hldvt.com/09/HLDVTAP09.pdf Hotel Information: http://www.hldvt.com/09/local.html Home Page: http://www.hldvt.com/09/index.html --00c09f8e5d614a865d04753db39a Content-Type: text/html; charset=windows-1252 Content-Transfer-Encoding: quoted-printable

IEEE International High Level Design<= /span>Validation and Test Works= hop 2009

=A0

November= 4-6, 2009

Grand Hyatt, San Francisco (Union Square)

Register at=A0http= ://www.hldvt.com/09/registration.html=A0before=A0October 7th=A0to receive discounted registration rate= s. Book your hotel room in the heart of San Francisco at a discounted rate = of $140.

=A0

For th= e past 13 years, IEEE International High Level Design Validation and Test W= orkshop has been a platform for addressing emerging challenges in verificat= ion and test methodologies for ICs and systems.=A0The workshop is an informal forum where EDA = tool developers, academics, and industrial practitioners get together to di= scuss contemporary issues in=A0verification, debug, synthesis, and test.

=A0This year's program will feature=85.

=B7=A0=A0=A0=A0=A0=A0Keynote Address by=A0Sunil R. Shenoy=A0- Vice President, Intel Architecture Group, a= nd General Manager, Microprocessor and Graphics Development - Intel Corpora= tion

=B7=A0=A0=A0=A0=A0=A0Seventeen Regular Paper= s

=B7=A0=A0=A0=A0=A0=A0Panel:=A0SystemC Why: To Design or to Verify? What experts say?

=B7=A0=A0=A0=A0=A0=A0Special Session:=A0<= i>Innovative Industrial Practices

=B7=A0=A0=A0=A0=A0=A0Three Invited Sessions:=

=B7=A0=A0=A0=A0=A0=A0RTL Validation and = Debug=

=B7=A0=A0=A0=A0=A0=A0High-Level Modeling = and Validation

=B7=A0=A0=A0=A0=A0=A0Post-Silicon Validat= ion and Debug

Helpful Links:

Advance Program:=A0= = http://www.hldvt.com/09/HLDVTAP09.pdf

Hotel Information:=A0=A0=A0

Home Page:=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0http://www.hldvt.com/09/index.html --00c09f8e5d614a865d04753db39a--