From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on yquem.inria.fr X-Spam-Level: *** X-Spam-Status: No, score=3.8 required=5.0 tests=DNS_FROM_RFC_POST,HTML_10_20, HTML_MESSAGE,SPF_NEUTRAL autolearn=disabled version=3.1.3 X-Original-To: caml-list@yquem.inria.fr Delivered-To: caml-list@yquem.inria.fr Received: from mail2-relais-roc.national.inria.fr (mail2-relais-roc.national.inria.fr [192.134.164.83]) by yquem.inria.fr (Postfix) with ESMTP id 32A92BBAF for ; Fri, 27 Mar 2009 21:38:22 +0100 (CET) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AqgCABLWzElKfVwZkGdsb2JhbACCVIoqiEU/AQEBAQkJDAcRA6psgQePYwEDAQODdAaHIw X-IronPort-AV: E=Sophos;i="4.38,434,1233529200"; d="scan'208";a="23421750" Received: from qw-out-2122.google.com ([74.125.92.25]) by mail2-smtp-roc.national.inria.fr with ESMTP; 27 Mar 2009 21:38:21 +0100 Received: by qw-out-2122.google.com with SMTP id 3so854164qwe.33 for ; Fri, 27 Mar 2009 13:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=MzlbD3645Zhp+oUTpIQ1MJFh6wAi9J5P6QdtWTjkh+g=; b=KaWdQ/7a2NDCXOv8FOaSbCQyyH35yBUIVhOT8+7yE9wR6qD1//CKSaX+u50Z6/BVpV HRi4zQbTG0dRgMBXqyQxpn9rAtOhrdvL5a8rFRCduYmEbM8r5nPb18fUd5c9bWAjvFqZ SiC9TFOnkXxOVENFiDJjhK//0yJSHcEJ6O3+0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=T5L0eqJFbOdyFcMZt0Z9wA6SnAwyNckXldpGc4lziESjaGw53m/tgxwHevz4TYWFd1 QaPUlwct0Rx/tZhNGovVph3RSOCRiiMcDWs7Xkc1RKb1vXAbDmHNNncBmIeDDDq/0xoF umM+3Sq2J5XvAtPfhTKL70pXScyItlfd7ji8I= MIME-Version: 1.0 Received: by 10.229.98.195 with SMTP id r3mr1219945qcn.88.1238186295892; Fri, 27 Mar 2009 13:38:15 -0700 (PDT) Date: Fri, 27 Mar 2009 15:38:15 -0500 Message-ID: <95bd0d720903271338q4f4c04b6vfb43073333ca2605@mail.gmail.com> Subject: 2nd call for papers: CFV'09, deadline April 22 From: Miroslav Velev To: puml-list@cs.york.ac.uk, reliable_computing@interval.louisiana.edu, procos@jiscmail.ac.uk, concurrency@cwi.nl, categories@mta.ca, moca-announce@list.it.uu.se, jml@cs.iastate.edu, ccp@sics.se, agents@cs.umbc.edu, csl@dbai.tuwien.ac.at, ipa@win.tue.nl, comlab@comlab.ox.ac.uk, theory-logic@cs.cmu.edu, logic-announce@uclink4.berkeley.edu, behavior@cs.ucsd.edu, petrinet@informatik.uni-hamburg.de, haskell@haskell.org, coq-club@pauillac.inria.fr, eacsl@dimi.uniud.it, se-group@cs.umn.edu, seworld@cs.colorado.edu, pvs@csl.sri.com, caml-list@inria.fr, fmics@inrialpes.fr, logic-list@helsinki.fi, seminar@iist.unu.edu, acl2@cs.utexas.edu, coalgebras@iti.cs.tu-bs.de, isabelle-users@cl.cam.ac.uk, nwpt-info@sool.ioc.ee, appsem@tcs.informatik.uni-muenchen.de, nvti-list@cwi.nl, formal-methods@cs.uidaho.edu, umsec-events@cs.umn.edu, lfcs-interest@dcs.ed.ac.uk, asci@twi.tudelft.nl, theorynt@listserv.nodak.edu, prog-lang@diku.dk, grin@di.unipi.it, components@artist-embedded.org, forum@prg.ox.ac.uk, stochver@cs.bham.ac.uk, "" Content-Type: multipart/alternative; boundary=0016364eed545523b604661fb6ec X-Spam: no; 0.00; solvers:01 solvers:01 lncs:01 lncs:01 freiburg:01 smt:01 bjorner:01 smt:01 freiburg:01 bjorner:01 disseminate:98 vale:98 minas:98 gerais:98 ric:98 --0016364eed545523b604661fb6ec Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Call for Papers CFV'09: Sixth International Workshop on Constraints in Formal Verification Grenoble, France, June 25, 2009. A satellite event of the 21st International Conference on Computer Aided Verification (CAV'09) CFV'09 web site: http://www.miroslav-velev.com/cfv09.html Abstract submission deadline: April 15 Paper submission deadline: April 22 Overview --------------------------------------------- Formal verification is of crucial significance in the development of hardware and software systems. In the last few years, tremendous progress was made in both the speed and capacity of constraint technology. Most notably, SAT solvers have become orders of magnitude faster and capable of handling problems that are orders of magnitude bigger, thus enabling the formal verification of more complex computer systems. As a result, the formal verification of hardware and software has become a promising area for research and industrial applications. The main goals of the Constraints in Formal Verification workshop are to bring together researchers from the CSP/SAT and the formal verification communities, to describe new applications of constraint technology to formal verification, to disseminate new challenging problem instances, and to propose new dedicated algorithms for hard formal verification problems. This workshop will be of interest to researchers from both academia and industry, working on constraints or on formal verification and interested in the application of constraints to formal verification. Scope --------------------------------------------- The scope of the workshop includes topics related to the application of constraint technology to formal verification, namely: - application of constraint solvers to hardware verification; - application of constraint solvers to software verification; - dedicated solvers for formal verification problems; - challenging formal verification problems. Delivery --------------------------------------------- The workshop is scheduled for June 25, 2009. It will be structured to allow ample time for discussion and demonstration of new tools and new problem instances. Submissions --------------------------------------------- Submissions should be in the LNCS format and in one of the following types: - a regular paper of up to 15 pages; - a short paper of up to 4 pages, describing an industrial experience. Workshop papers should be submitted electronically in pdf format. Papers should be formatted using the Lecture Notes in Computer Science (LNCS) style. Paper submissions should be e-mailed to the workshop chairs at: mvelev@gmail.com Important Dates --------------------------------------------- The important dates for the workshop are as follows: - abstract submission deadline: April 15 - paper submission deadline: April 22 - notification of acceptance: May 10 - camera-ready version deadline: May 31 - workshop date: June 25 Invited Speakers --------------------------------------------- Bernd Becker, University of Freiburg, Germany Talk title: SAT and SMT Solving in a Multi-Core Environment Nikolaj Bjorner, Microsoft Research, U.S.A. Talk title: SMT Solving and Applications of Bit-Level Constraints Workshop Chair --------------------------------------------- Miroslav Velev, Aries Design Automation, U.S.A. Masahiro Fujita, University of Tokyo, Japan Program Committee -------------------------------------------- Jay Bhadra, Freescale, U.S.A. S=E9rgio Vale Aguiar Campos, Universidade Federal de Minas Gerais, Brazil Maciej Ciesielski, University of Massachusetts, U.S.A. Goerschwin Fey, University of Bremen, Germany Alex D. Groce, NASA-JPL, U.S.A. Michael Hsiao, Virginia Tech, U.S.A. Chung-Yang (Ric) Huang, National Taiwan University, Taiwan John Franco, University of Cincinnati, U.S.A. Priyank Kalla, University of Utah, U.S.A. Shin-ichi Minato, Hokkaido University, Japan Steve Prestwich, University College Cork, Ireland Andreas Veneris, University of Toronto, Canada --0016364eed545523b604661fb6ec Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

Call for Papers

CFV'09:=A0 Sixth International Workshop on Constraints in Formal Verification

Grenoble, France, June 25, 2009.
A satellite event of the 21st Intern= ational Conference on
Computer Aided Verification (CAV'09)


CFV'09 web site: http://www.miroslav-velev.com/cfv09.html


Abstract submission deadline:=A0 April 15
Paper submission deadli= ne:=A0 April 22


Overview
---------------------------------------------
Formal = verification is of crucial significance in the development of
hardware a= nd software systems. In the last few years, tremendous
progress was made= in both the speed and capacity of constraint
technology. Most notably, SAT solvers have become orders of magnitude
fa= ster and capable of handling problems that are orders of magnitude
bigge= r, thus enabling the formal verification of more complex computer
system= s. As a result, the formal verification of hardware and software
has become a promising area for research and industrial applications.
Th= e main goals of the Constraints in Formal Verification workshop are
to b= ring together researchers from the CSP/SAT and the formal
verification c= ommunities, to describe new applications of constraint
technology to formal verification, to disseminate new challenging
proble= m instances, and to propose new dedicated algorithms for hard
formal ver= ification problems.
This workshop will be of interest to researchers fro= m both academia
and industry, working on constraints or on formal verification and
inter= ested in the application of constraints to formal verification.


Scope
---------------------------------------------
The scope = of the workshop includes topics related to the application
of constraint= technology to formal verification, namely:
- application of constraint = solvers to hardware verification;
- application of constraint solvers to software verification;
- dedicate= d solvers for formal verification problems;
- challenging formal verific= ation problems.


Delivery
---------------------------------------------
The wor= kshop is scheduled for June 25, 2009. It will be
structured to allow amp= le time for discussion and demonstration of new
tools and new problem in= stances.


Submissions
---------------------------------------------
Subm= issions should be in the LNCS format and in one of the following types:
= - a regular paper of up to 15 pages;
- a short paper of up to 4 pages, d= escribing an industrial experience.
Workshop papers should be submitted electronically in pdf format.
Papers= should be formatted using the Lecture Notes in Computer Science
(LNCS) = style.
Paper submissions should be e-mailed to the workshop chairs at: <= br> mvelev@gmail.com<= /p>


Important Dates
---------------------------------------------
= The important dates for the workshop are as follows:
- abstract submissi= on deadline:=A0 April 15
- paper submission deadline:=A0 April 22
- n= otification of acceptance:=A0 May 10
- camera-ready version deadline:=A0 May 31
- workshop date:=A0 June 25


Invited Speakers
---------------------------------------------Bernd Becker, University of Freiburg, Germany
=A0 Talk title: SAT and S= MT Solving in a Multi-Core Environment

Nikolaj Bjorner,=20 Microsoft Research, U.S.A.
=A0=A0 Talk title: SMT Solving and Applications of Bit-Level Constraints

Workshop Chair
---------------------------------------------
Miros= lav Velev, Aries Design Automation, U.S.A.

Masahiro Fujita, University of Tokyo, Japan

=A0


Program Committee
--------------------------------------------Jay Bhadra, Freescale, U.S.A.

S=E9rgio Vale Aguiar Campos, Universidade Federal de Minas Gerais, Brazi= l

Maciej Ciesielski, University of Massachusetts, U.S.A.

Goerschwin Fey, University of Bremen, Germany

Alex D. Groce, NASA-JPL, U.S.A.

Michael Hsiao, Virginia Tech, U.S.A.

Chung-Yang (Ric) Huang, National Taiwan University, Taiwan

John Franco, University of Cincinnati, U.S.A.

Priyank Kalla, University of Utah, U.S.A.

Shin-ichi Minato, Hokkaido University, Japan

Steve Prestwich, University College Cork, Ireland

Andreas Veneris, University of Toronto, Canada

=A0

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