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Mon, 26 Feb 2018 00:56:46 -0800 (PST) MIME-Version: 1.0 References: <20180225161430.zkfpkihg7jyxs5cg@annexia.org> <3516931D-FCEF-4DDB-9FF7-11D3345B6D6C@orbitalfox.eu> In-Reply-To: From: Xavier Leroy Date: Mon, 26 Feb 2018 08:56:35 +0000 Message-ID: To: "caml-list@inria.fr" Content-Type: multipart/alternative; boundary="001a11453a7294a73c056619b0b8" Subject: Re: [Caml-list] Status of the OCaml RISC-V port --001a11453a7294a73c056619b0b8 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, Feb 25, 2018 at 11:36 PM Nicol=C3=A1s Ojeda B=C3=A4r < nicolas.ojeda.bar@lexifi.com> wrote: > > When the time comes, the patch will be submitted as a github PR and > everyone is warmly invited to take part in that discussion. > > Absolutely. Just to reinforce what's been said already: there is no doubt in my mind that the RISC-V back-end will be part of the core OCaml distribution. What is not completely decided is when it will be merged. I'm looking forward to playing with the first RISC-V hardware implementation, thanks to OCaml Labs. It's good to know about the QEMU-based virtual environment mentioned by Rich Jones. - Xavier Leroy > And of course, PRs are also welcome anytime at > https://github.com/nojb/riscv-ocaml ! > > Best wishes, > Nicol=C3=A1s > > > On Sun, Feb 25, 2018 at 10:35 PM, SP wrote: > >> >> >> On 25 February 2018 19:29:45 GMT+00:00, David Allsopp < >> dra-news@metastack.com> wrote: >> >will hopefully start the process of upstreaming the RISC-V patches. >> >> Will you be looking for help from the wider community for this? >> >> -- >> SP >> > > --001a11453a7294a73c056619b0b8 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Sun, Feb 25= , 2018 at 11:36 PM Nicol=C3=A1s Ojeda B=C3=A4r <nicolas.ojeda.bar@lexifi.com> wrote:

When the time co= mes, the patch will be submitted as a github PR and everyone is warmly invi= ted to take part in that discussion.


Absolutely.=C2=A0 Just to reinforce what's been sa= id already: there is no doubt in my mind that the RISC-V back-end will be p= art of the core OCaml distribution.=C2=A0 What is not completely decided is= when it will be merged.=C2=A0 I'm looking forward to playing with the = first RISC-V hardware implementation, thanks to OCaml Labs.=C2=A0 It's = good to know about the QEMU-based virtual environment mentioned by Rich Jon= es.

- Xavier Leroy
=C2=A0
And of course, PRs are = also welcome anytime at https://github.com/nojb/riscv-ocaml !

Best wishes,
Nicol=C3=A1s
=


On= Sun, Feb 25, 2018 at 10:35 PM, SP <sp@orbitalfox.eu> wrote:<= br>


On 25 February 2018 19:29:45 GMT+00:00, David Allsopp <dra-news@metastack.com> w= rote:
>will hopefully start the process of upstreaming the RISC-V patches.

Will you be looking for help from the wider community for this?

--
=C2=A0 =C2=A0 SP

--001a11453a7294a73c056619b0b8--