From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (from majordomo@localhost) by pauillac.inria.fr (8.7.6/8.7.3) id QAA09351; Fri, 9 Jul 2004 16:35:04 +0200 (MET DST) X-Authentication-Warning: pauillac.inria.fr: majordomo set sender to owner-caml-list@pauillac.inria.fr using -f Received: from nez-perce.inria.fr (nez-perce.inria.fr [192.93.2.78]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id QAA09919 for ; Fri, 9 Jul 2004 16:35:03 +0200 (MET DST) Received: from outbound28-2.lax.untd.com (outbound28-2.lax.untd.com [64.136.28.160]) by nez-perce.inria.fr (8.12.10/8.12.10) with SMTP id i69EZ1EV015157 for ; Fri, 9 Jul 2004 16:35:01 +0200 Received: from outbound28-2.lax.untd.com (smtp03.lax.untd.com [10.130.24.123]) by smtpout01.lax.untd.com with SMTP id AABAQ7MHPABAHVZA for (sender ); Fri, 9 Jul 2004 07:34:21 -0700 (PDT) Received: (qmail 3352 invoked from network); 9 Jul 2004 14:34:05 -0000 Received: from unknown (HELO vangogh) (66.52.241.30) by smtp03.lax.untd.com with SMTP; 9 Jul 2004 14:34:05 -0000 From: "Brandon J. Van Every" To: "caml" Subject: RE: [Caml-list] tail recursion and register poor Intel architecture Date: Fri, 9 Jul 2004 07:44:17 -0700 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Priority: 3 (Normal) X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook IMO, Build 9.0.6604 (9.0.2911.0) In-Reply-To: <40EE40F5.4010406@bik-gmbh.de> X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1409 Importance: Normal X-ContentStamp: 7:3:2616356594 X-UNTD-OriginStamp: CI84cOLHFqh7Zd2QWkwvEFvwyO3T/pIsPQZphDk9MRgPBXTadta+j9uCO5UjgW7F X-Miltered: at nez-perce with ID 40EEAD15.000 by Joe's j-chkmail (http://j-chkmail.ensmp.fr)! X-Loop: caml-list@inria.fr X-Spam: no; 0.00; brandon:99 caml-list:01 recursion:01 florian:01 hars:01 brandon:99 doubles:01 caml-list:01 bayesian:01 crap:01 crap:01 -bit:01 -bit:01 anyways:02 float:02 Sender: owner-caml-list@pauillac.inria.fr Precedence: bulk Florian Hars wrote: > Brandon J. Van Every wrote: > > Well, you could pass the first 6 integer arguments via the normal > > registers, the first 8 floating point arguments via the x87 > > FPU, and the > > next 8 integer or float arguments via the XMM registers. > > But this will give you different results for your > computations, depending on > argument ordering (if you push an argument from the last x87 > register to the first XMM register, it loses 16 bits). You are worrying about 80-bit Intel internal precision vs. the 64-bit IEEE storage format? That's a little too anal for my tastes. If you store your results as 64-bit doubles at some point, you're going to lose that internal precision anyways. Cheers, www.indiegamedesign.com Brand*n Van Every S*attle, WA Praise Be to the caml-list Bayesian filter! It blesseth my postings, it is evil crap! evil crap! evil crap! ------------------- To unsubscribe, mail caml-list-request@inria.fr Archives: http://caml.inria.fr Bug reports: http://caml.inria.fr/bin/caml-bugs FAQ: http://caml.inria.fr/FAQ/ Beginner's list: http://groups.yahoo.com/group/ocaml_beginners