From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (from majordomo@localhost) by pauillac.inria.fr (8.7.6/8.7.3) id PAA07166; Mon, 19 Aug 2002 15:08:10 +0200 (MET DST) X-Authentication-Warning: pauillac.inria.fr: majordomo set sender to owner-caml-list@pauillac.inria.fr using -f Received: from concorde.inria.fr (concorde.inria.fr [192.93.2.39]) by pauillac.inria.fr (8.7.6/8.7.3) with ESMTP id PAA07219 for ; Mon, 19 Aug 2002 15:08:09 +0200 (MET DST) Received: from comtv.ru (comtv.ru [217.10.32.4]) by concorde.inria.fr (8.11.1/8.11.1) with ESMTP id g7JD88T10516; Mon, 19 Aug 2002 15:08:08 +0200 (MET DST) Received: from [10.0.66.9] ([10.0.66.9] verified) by comtv.ru (CommuniGate Pro SMTP 3.5.9) with ESMTP-TLS id 4147096; Mon, 19 Aug 2002 17:08:07 +0400 Date: Mon, 19 Aug 2002 17:07:33 +0400 (MSD) From: malc X-X-Sender: malc@home.oyster.ru To: Xavier Leroy cc: William Chesters , Subject: Re: float array alignment; was Re: [Caml-list] Bigarray access speed In-Reply-To: <20020819145605.A6276@pauillac.inria.fr> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: owner-caml-list@pauillac.inria.fr Precedence: bulk On Mon, 19 Aug 2002, Xavier Leroy wrote: > malc writes: > > To get maximal speed of the inner loops data needs to be naturally > > aligned. OCaml does nothing to enforce it for non-big arrays. Bigarrays on > > the other hand are mmaped(4k on IA32) and you get perfectly aligned data > > for free. I was thinking that maybe Array can be extended with > > make[create]_aligned, for speed/space tradeoff. > > As William Chester said, allocating 8-aligned arrays isn't really > hard, but keeping them 8-aligned across copying collection, > compaction, and structured I/O is quite a pain. > > My experiments indicate that the lack of alignment on float arrays > (or more precisely the fact that they are 4-aligned instead of > 8-aligned) has negligible impact on performance for the IA32 (Pentium) > and PowerPC processors, but non-negligible for SPARC and MIPS. > And of course on a 64-bit architecture the problem goes away because > everything in the Caml heap is then 8-aligned. Since I expect IA32 > and PowerPC to remain dominant until we massively switch to 64-bit > processors, there's no urgent need to do something about float array > alignment. IA32 is now much bigger family, and unlucky owners of AMD 7th generation machines, such as myself, do pay a price for unaligned double precission float accesses. -- mailto:malc@pulsesoft.com ------------------- To unsubscribe, mail caml-list-request@inria.fr Archives: http://caml.inria.fr Bug reports: http://caml.inria.fr/bin/caml-bugs FAQ: http://caml.inria.fr/FAQ/ Beginner's list: http://groups.yahoo.com/group/ocaml_beginners