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* [COFF] [TUHS] 68k prototypes & microcode
       [not found]                 ` <20210204013356.GA16541@mcvoy.com>
@ 2021-02-04 15:26                   ` crossd
  2021-02-05  9:09                   ` peter
  2021-02-05 14:36                   ` [COFF] Architectures -- was " clemc
  2 siblings, 0 replies; 10+ messages in thread
From: crossd @ 2021-02-04 15:26 UTC (permalink / raw)


On Wed, Feb 3, 2021 at 8:34 PM Larry McVoy <lm at mcvoy.com> wrote:

> I have to admit that I haven't looked at ARM assembler, the M1 is making
> me rethink that.  Anyone have an opinion on where ARM lies in the pleasant
> to unpleasant scale?
>

Redirecting to "COFF" as this is drifting away from Unix.

I have a soft spot for ARM, but I wonder if I should. At first blush, it's
a pleasant RISC-ish design: loads and stores for dealing with memory,
arithmetic and logic instructions work on registers and/or immediate
operands, etc. As others have mentioned, there's an inline barrel shifter
in the ALU that a lot of instructions can take advantage of in their second
operand; you can rotate, shift, etc, an immediate or register operand while
executing an instruction: here's code for setting up page table entries for
an identity mapping for the low part of the physical address space (the
root page table pointer is at phys 0x40000000):

        MOV     r1, #0x0000
        MOVT    r1, #0x4000
        MOV     r0, #0
.Lpti:  MOV     r2, r0, LSL #20
        ORR     r2, r2, r3
        STR     r2, [r1], #4
        ADD     r0, r0, #1
        CMP     r0, #2048
        BNE     .Lpti

(Note the `LSL #20` in the `MOV` instruction.)

32-bit ARM also has some niceness for conditionally executing instructions
based on currently set condition codes in the PSW, so you might see
something like:

1:      CMP     r0, #0
        ADDNE   r1, r1, #1
        SUBNE   r0, r0, #1
        BNE     1b

The architecture tends to map nicely to C and similar languages (e.g.
Rust). There is a rich set of instructions for various kinds of arithmetic;
for instance, they support saturating instructions for DSP-style code. You
can push multiple registers onto the stack at once, which is a little odd
for a RISC ISA, but works ok in practice.

The supervisor instruction set is pretty nice. IO is memory-mapped, etc.
There's a co-processor interface for working with MMUs and things like it.
Memory mapping is a little weird, in that the first-level page table isn't
the same second-level tables: the first-level page table maps the 32-bit
address space into 1MiB "sections", each of which is described by a 32-bit
section descriptor; thus, to map the entire 4GiB space, you need 4096 of
those in 16KiB of physically contiguous RAM. At the second-level, 4KiB page
frames map page into the 1MiB section at different granularities; I think
the smallest is 1KIB (thus, you need 1024 32-bit entries). To map a 4KiB
virtual page to a 4KiB PFN, you repeat the relevant entry 4 times in the
second-level page. It ends up being kind of annoying. I did a little toy
kernel for ARM32 and ended up deciding to use 16KiB pages (basically, I map
4x4KiB contiguous pages) so I could allocate a single sized structure for
the page tables themselves.

Starting with the ARMv8 architecture, it's been split into 32-bit aarch32
(basically the above) and 64-bit aarch64; the latter has expanded the
number and width of general purpose registers, one is a zero register in
some contexts (and I think a stack pointer in others? I forget the
details). I haven't played around with it too much, but looked at it when
it came out and thought "this is reasonable, with some concessions for
backwards compatibility." They cleaned up the paging weirdness mentioned
above. The multiple push instruction has been retired and replaced with a
"push a pair of adjacent registers" instruction; I viewed that as a
concession between code size and instruction set orthogonality.

So...Overall quite pleasant, and far better than x86_64, but with some
oddities.

        - Dan C.
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* [COFF] [TUHS] 68k prototypes & microcode
       [not found]                     ` <alpine.BSF.2.21.9999.2102051312440.70858@aneurin.horsfall.org>
@ 2021-02-05  2:53                       ` lm
  0 siblings, 0 replies; 10+ messages in thread
From: lm @ 2021-02-05  2:53 UTC (permalink / raw)


On Fri, Feb 05, 2021 at 01:16:08PM +1100, Dave Horsfall wrote:
> [ Directing to COFF, where it likely belongs ]
> 
> On Thu, 4 Feb 2021, Arthur Krewat wrote:
> 
> >>-- Dave, wondering whether anyone has ever used every VAX instruction
> >
> >Or every VMS call, for that matter. ;)
> 
> Urk...  I stayed away from VMS as much as possible (I had a network of
> PDP-11s to play with), although I did do a device driver course; dunno why.

Me too, though I did use Eunice, it was a lonely place, it did not let
me see who was on VMS.  I was the only one.  A far cry from BSD where
wall went to everyone and talk got you a screen where you talked.



^ permalink raw reply	[flat|nested] 10+ messages in thread

* [COFF] [TUHS] AT&T 3B1 - Emulation available
       [not found]           ` <CAC20D2M_33YdQyuHdb7EM-UVNcdM0TXz9eJXpTftHekWxK0=Dg@mail.gmail.com>
@ 2021-02-05  8:53             ` peter
  2021-02-05 17:41               ` [COFF] " cym224
       [not found]             ` <27567.1612399305@hop.toad.com>
  1 sibling, 1 reply; 10+ messages in thread
From: peter @ 2021-02-05  8:53 UTC (permalink / raw)


On 2021-Feb-03 09:58:37 -0500, Clem Cole <clemc at ccc.com> wrote:
>but the original released (distributed - MC68000) part was binned at 8 and
>10

There was also a 4MHz version.  I had one in my MEX68KECB but I'm not
sure if they were ever sold separately.  ISTR I got the impression
that it was a different (early) mask or microcode variant because some
of the interface timings weren't consistent with the 8/10 MHz versions
(something like one of the bus timings was a clock-cycle slower).

>as were the later versions with the updated paging microcode called the
>MC68010 a year later.   When the 68020 was released Moto got the speeds up
>to 16Mhz and later 20.  By the '040 I think they were running at 50MHz

I also really liked the M68k architecture.  Unfortunately, as with the
M6800, Motorola lost out to Intel's inferior excuse for an architecture.

Moving more off-topic, M68k got RISC-ified as the ColdFire MCF5206.
That seemed (to me) to combine the feel of the M68k with the
clock/power gains from RISC.  Unfortunately, it didn't take off.

-- 
Peter Jeremy
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* [COFF] [TUHS] 68k prototypes & microcode
       [not found]                 ` <20210204013356.GA16541@mcvoy.com>
  2021-02-04 15:26                   ` crossd
@ 2021-02-05  9:09                   ` peter
  2021-02-05 14:36                   ` [COFF] Architectures -- was " clemc
  2 siblings, 0 replies; 10+ messages in thread
From: peter @ 2021-02-05  9:09 UTC (permalink / raw)


On 2021-Feb-03 17:33:56 -0800, Larry McVoy <lm at mcvoy.com> wrote:
>The x86 stuff is about as far away from PDP-11 as you can get.  Required
>to know it, but so unpleasant.

Warts upon warts upon warts.  The complete opposite of orthogonal.

>I have to admit that I haven't looked at ARM assembler, the M1 is making
>me rethink that.  Anyone have an opinion on where ARM lies in the pleasant
>to unpleasant scale?

I haven't spent enough time with ARM assembler to form an opinion but
there are a number of interesting interviews with the designers on YT:
* A set of videos by Sophie Wilson (original designer) starting at
  https://www.youtube.com/watch?v=jhwwrSaHdh8
* A history of ARM by Dave Jaggar (redesigner) at
  https://www.youtube.com/watch?v=_6sh097Dk5k

If you don't want to pony up for a M1, there are a wide range of ARM
SBCs that you could experiment with.

-- 
Peter Jeremy
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^ permalink raw reply	[flat|nested] 10+ messages in thread

* [COFF] Architectures -- was [TUHS] 68k prototypes & microcode
       [not found]                 ` <20210204013356.GA16541@mcvoy.com>
  2021-02-04 15:26                   ` crossd
  2021-02-05  9:09                   ` peter
@ 2021-02-05 14:36                   ` clemc
  2021-02-05 14:56                     ` [COFF] [SPAM] " lm
  2021-02-05 19:16                     ` [COFF] " athornton
  2 siblings, 2 replies; 10+ messages in thread
From: clemc @ 2021-02-05 14:36 UTC (permalink / raw)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
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Moved to COFF  - and I should prefix this note with a strongly worded --
these are my own views and do not necessarily follow my employers (and
often have not, as some of you know that have worked with me in the past).

On Wed, Feb 3, 2021 at 8:34 PM Larry McVoy <lm at mcvoy.com> wrote:

> The x86 stuff is about as far away from PDP-11 as you can get.  Required
> to know it, but so unpleasant.
>
BTW: Once again we 100% agree *on the architecture part of* *the discussion*.
And frankly pre-386 days, I could not think how anyone would come up with
it.  As computer architecture it is terrible, how did so many smart people
come up with such?  It defies everything we are taught about 'good'
computer architectural design.  But ....   after all of the issues with the
ISA's of Vax and the x86/INTEL*64 *vs.* Alpha --- is how I came to the
conclusion, *architecture does not matter nearly as much as economics and
we need to get over it and stop whining.  * Or in Christensen's view, a new
growing market is often made from a product that has technically not as
good as the one in the original mainstream market but has some value to the
new group of people.

x86 (and in particular once the 386 added linear 32 bit addressing), even
though DOS/Windows sucked compared to SunOS (or whatever), the job (work)
that the users needed to do was performed to the customer's satisfaction *and
for a lot less.*  The ISVs could run their codes there and >>they<< sell
more copies of their code which is what they care about.  The end-users,
really just care about getting a job done.

What was worse was at the time, it was the ISV's keep their own prices
higher on the 'high-value platform' - which makes the cost of those
platforms ever higher.  During the Unix wars, this fact was a huge issue.
The same piece of SW for a Masscomp would cause 5-10 more than a Sun -- why
we were considered a minicomputer and Sun was a workstation.   Same 10MHz
68000 inside (we had a better compiler so we ran 20% faster).   This was
because the ISV's classified Masscomp's competition was considered the Vax
8600; not Sun and Apollo -- sigh.

In the end, the combination of x86 and MSFT did it to Sun.   For example,
my college roommates (who were trained on the first $100K
architecture/drawing 3D systems developed at CMU on PDP-11/Unix and Triple
Drip Graphic's Wonder) Wintel running a 'boxed' AutoCAD was way more
economical than a Sun box with a custom architecture package -- economics
won, even though the solution was technically not as good.    Another form
of the same issue did you ever try to write a technical >>publication<<
with Word (not a letter or a memo) -- it sucks -- The pro's liked FrameMaker
and other 'authoring tools' (hey I think even Latex and Troff are -- much '
better' for the author) -- but Frame costs way more and Word, so what do
the publishers want -- ugh Word DOC format [ask Steinhart about this issue,
he lived it a year ago].

In the case of the Arm, Intel #$%^'ed 101-15 yrs ago up when Jobs said he
wanted a $20 processor for what would become the iPhone and our execs told
him to take a hike (we were making too much money with high margin
Window's) boxes.   At the time, Arm was 'not as good' - but it had two
properties Jobs cared about (better power - although at the time Arm was
actually not much better than the laptop x86s, but Apple got Samsung to
make/sell parts at less than $20 -- i.e. economics).

Again, I'm not a college professor.  I'm an engineer that builds real
computer systems that sometimes people (even ones like the folks that read
this list) want to/have wanted buy.   As much as I like to use sold
architecture principle to guide things, the difference is I know be
careful.  Economics is really the higher bit.  What the VAX engineers at
DEC or the current INTEL*64 folks (like myself) was/is not what some of the
same engineers did with Alpha -- today, we have to try to figure out how to
make the current product continue to be economically attractive [hence the
bazillion new instructions that folks like Paul W in the compiler team
figure out how to exploit, so the ISV's codes run better and can sell more
copies and we sell more chips to our customers to sell to end users].

But like Jobs's, DEC management got caught up in the high margin game, and
ignored the low end (I left Compaq after I managed to build the $1K Alpha
which management blew off -- it could be sold at 45% margins like the Alpha
TurboLaser or 4x00 series).   Funny, one of the last things I had proposed
at Masscomp in the early 80s before I went to Stellar, was a low-end system
(also < $1K) and Masscomp management wanted to part of it -- it would have
meant competing with Sun and eventually the PC.

FWIW:  Intel >>does<< know how to make a $20 SOC, but the margins will
suck.  The question is what will management want to?   I really don't
know.  So far, we have liked the server chip margins (don't forget Intel
made more $s last year than it ever has - even in the pandemic).

I feel a little like Dr Seuss'  'Onceler' in the Lorax story ... if Arm can
go upscale from the phone platform who knows what will happen - Bell's Law
predicts Arm displaces INTEL*64:

“Approximately every decade a new computer class forms as a new “minimal”
computer either through using fewer components or use of a small fractional
part of the state-of-the-art chips.”

FWIW:  Bell basically has claimed a technical point, based on Christenson's
observation; the 'lessor' technology will displace the 'better one.'   Or
as I say it, sophisticated architecture always losses to better economics.
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* [COFF] [SPAM] Re: Architectures -- was [TUHS] 68k prototypes & microcode
  2021-02-05 14:36                   ` [COFF] Architectures -- was " clemc
@ 2021-02-05 14:56                     ` lm
  2021-02-05 18:31                       ` david
  2021-02-05 22:02                       ` dave
  2021-02-05 19:16                     ` [COFF] " athornton
  1 sibling, 2 replies; 10+ messages in thread
From: lm @ 2021-02-05 14:56 UTC (permalink / raw)


On Fri, Feb 05, 2021 at 09:36:20AM -0500, Clem Cole wrote:
> FWIW:  Intel >>does<< know how to make a $20 SOC, but the margins will
> suck.  The question is what will management want to?   I really don't
> know.  So far, we have liked the server chip margins (don't forget Intel
> made more $s last year than it ever has - even in the pandemic).

I think Intel is sort of in the same place Sun was.  Fat, dumb, and
happy with the profits they are making and can't see what is coming.

It just didn't make sense to have $20,000 Sun workstations when a $2,000
PC was at least half as good.  I advocated for SunOS on x86, to me,
it was the operating system that delivered the value, everything just
worked on SunOS, for any other OS you were doing the configure dance.
Offer SunOS on x86 and capture the low end market.  The East coast Sun
did the road runner but West coast Sun sneered at it, patches for x86
were not processed very fast, if at all.  It's a shame.

If Intel doesn't want to make money off of the cheap, but very high
volume, $20 SOC, Apple has shown that it has the chops to make a cheap,
fast, and power sipping M1 chip.  Pretty impressive and if I were Intel,
I'd be nervous.  Apple has shown they can switch architectures pretty
painlessly repeatedly.  The x86 lock in isn't much of a lock in these
days.


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [COFF] AT&T 3B1 - Emulation available
  2021-02-05  8:53             ` [COFF] [TUHS] AT&T 3B1 - Emulation available peter
@ 2021-02-05 17:41               ` cym224
  0 siblings, 0 replies; 10+ messages in thread
From: cym224 @ 2021-02-05 17:41 UTC (permalink / raw)


On 02/05/21 03:53, Peter Jeremy via COFF wrote (in part):
> Moving more off-topic, M68k got RISC-ified as the ColdFire MCF5206.
> That seemed (to me) to combine the feel of the M68k with the 
> clock/power gains from RISC. Unfortunately, it didn't take off.

I know not how much of the embedded market used ColdFire but I recall a 
lot of our embedded projects used ColdFire.

N.


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [COFF] [SPAM] Re: Architectures -- was [TUHS] 68k prototypes & microcode
  2021-02-05 14:56                     ` [COFF] [SPAM] " lm
@ 2021-02-05 18:31                       ` david
  2021-02-05 22:02                       ` dave
  1 sibling, 0 replies; 10+ messages in thread
From: david @ 2021-02-05 18:31 UTC (permalink / raw)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
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> On Feb 5, 2021, at 6:56 AM, Larry McVoy <lm at mcvoy.com> wrote:
> 
> If Intel doesn't want to make money off of the cheap, but very high
> volume, $20 SOC, Apple has shown that it has the chops to make a cheap,
> fast, and power sipping M1 chip.  Pretty impressive and if I were Intel,
> I'd be nervous.  Apple has shown they can switch architectures pretty
> painlessly repeatedly.  The x86 lock in isn't much of a lock in these
> days.

On my morning walk with a friend we discussed what iNtel is going to 
do about the M1 and coming M2, M3 chips from Apple. His contention
was that iNtel can’t do much because each vendor will want a different
configuration of the chip; more cores fewer GPU’s, more GPU’s fewer
cores, more of both, more/less RAM on board, etc.

It is unlikely that a SOC from iNtel can’t meet this varied selection so
it is unlikely to move into that market. It does have a solid lock on the
server market and it may just stick with that for the foreseeable future. 
The problem is that if the newer M2/M3 chips can perform at server
performance while retaining the low power consumption that the M1
has done, iNtel may see that its best days are past.

Disclaimer: I’ve got an M1 mini, and I have to say it is stunningly fast.

	David





^ permalink raw reply	[flat|nested] 10+ messages in thread

* [COFF] Architectures -- was [TUHS] 68k prototypes & microcode
  2021-02-05 14:36                   ` [COFF] Architectures -- was " clemc
  2021-02-05 14:56                     ` [COFF] [SPAM] " lm
@ 2021-02-05 19:16                     ` athornton
  1 sibling, 0 replies; 10+ messages in thread
From: athornton @ 2021-02-05 19:16 UTC (permalink / raw)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 2237 bytes --]



> On Feb 5, 2021, at 7:36 AM, Clem Cole <clemc at ccc.com> wrote:
> 
> I feel a little like Dr Seuss'  'Onceler' in the Lorax story ... if Arm can go upscale from the phone platform who knows what will happen - Bell's Law predicts Arm displaces INTEL*64: 
> “Approximately every decade a new computer class forms as a new “minimal” computer either through using fewer components or use of a small fractional part of the state-of-the-art chips.” 
> 
> FWIW:  Bell basically has claimed a technical point, based on Christenson's observation; the 'lessor' technology will displace the 'better one.'   Or as I say it, sophisticated architecture always losses to better economics.

…

As it happens, I got my M1 Macbook Air on Tuesday.

Nothing seems slower than my 2018 Air, which is kind of astonishing given that I know most of the applications are still Intel-native and being run under Rosetta emulation (and x86_64 is not a particularly easy architecture to emulate).

And, oh my goodness, the battery life.

I’ve been unplugging it first thing in the morning, and I don’t have to plug it in again until 2PM-ish.  I have Slack and Discord open, both of which were horrendous CPU hogs on the Intel Air, and am doing light Python development with it, albeit not tons of compilation.  My Intel Air’s CPU temperature was usually 65C, going up to 80C if I did a video call.  The M1 is at 32.2C, which given that the ambient temperature in my office is probably 22C (Tucson, during the winter, with the doors and windows open), is pretty impressive, especially since it has no fan.  Last night it did a 3-1/2 hour video call from the battery without any complaint whatsoever.

So…arm64 is cheap, fast, and remarkaby power-efficient[*].  I am impressed.

Adam

[*] not that I didn’t know this before.  The first four items at https://mvsevm.fsf.net/ <https://mvsevm.fsf.net/> are running on a single Pi 3B+ running 64-bit Ubuntu.  It doesn’t have a battery, but I think it’s drawing at most 5W, and the CPU temperature is 52C (also passively cooled).
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* [COFF] [SPAM] Re: Architectures -- was [TUHS] 68k prototypes & microcode
  2021-02-05 14:56                     ` [COFF] [SPAM] " lm
  2021-02-05 18:31                       ` david
@ 2021-02-05 22:02                       ` dave
  1 sibling, 0 replies; 10+ messages in thread
From: dave @ 2021-02-05 22:02 UTC (permalink / raw)


On Fri, 5 Feb 2021, Larry McVoy wrote:

> I think Intel is sort of in the same place Sun was.  Fat, dumb, and 
> happy with the profits they are making and can't see what is coming.

I guess we'll find out soon enough; there is a history of companies "too 
big to fail" of failing.

> It just didn't make sense to have $20,000 Sun workstations when a $2,000 
> PC was at least half as good.  I advocated for SunOS on x86, to me, it 
> was the operating system that delivered the value, everything just 
> worked on SunOS, for any other OS you were doing the configure dance. 
> Offer SunOS on x86 and capture the low end market.  The East coast Sun 
> did the road runner but West coast Sun sneered at it, patches for x86 
> were not processed very fast, if at all.  It's a shame.

I actually got to play with a Road Runner at a Sun conference (its 
hostname was "milpitas" of course) and came away impressed that one of the 
best OSes ran on the worst possible architecture :-)

> If Intel doesn't want to make money off of the cheap, but very high 
> volume, $20 SOC, Apple has shown that it has the chops to make a cheap, 
> fast, and power sipping M1 chip.  Pretty impressive and if I were Intel, 
> I'd be nervous.  Apple has shown they can switch architectures pretty 
> painlessly repeatedly.  The x86 lock in isn't much of a lock in these 
> days.

Well, when you're big enough to be able to make both your own HW and SW 
then things will go smoothly (which is why my MacBook works so well).  I 
look forward to Brian Krebs' "Patch Tuesday" announcements; I can only 
think that it's some form of "Stockholm Syndrome" despite there being many 
free alternatives.

Heck, I remember in the days of the Pee-Cee "grey imports" that if it 
didn't run Flight Simulator then it was illegal; shortly afterwards if it 
didn't run FS then nobody would buy it...

Ah, "schadenfreude" is such a beautiful word :-)

-- Dave


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2021-02-05  2:53                       ` [COFF] [TUHS] 68k prototypes & microcode lm
     [not found]                 ` <20210204013356.GA16541@mcvoy.com>
2021-02-04 15:26                   ` crossd
2021-02-05  9:09                   ` peter
2021-02-05 14:36                   ` [COFF] Architectures -- was " clemc
2021-02-05 14:56                     ` [COFF] [SPAM] " lm
2021-02-05 18:31                       ` david
2021-02-05 22:02                       ` dave
2021-02-05 19:16                     ` [COFF] " athornton

Computer Old Farts Forum

This inbox may be cloned and mirrored by anyone:

	git clone --mirror https://inbox.vuxu.org/coff

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V1 coff coff/ https://inbox.vuxu.org/coff \
		coff@minnie.tuhs.org
	public-inbox-index coff

Example config snippet for mirrors.
Newsgroup available over NNTP:
	nntp://inbox.vuxu.org/vuxu.archive.coff


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git