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* Re: [COFF] Encoding an ISA: Random Logic vs. Control Stores
       [not found] <010901d7e5c1$4a0c7c20$de257460$@gmail.com>
@ 2021-11-30 16:47 ` Clem Cole
  2021-11-30 19:04   ` Bakul Shah
       [not found] ` <em13f2dbb4-13fd-4d28-b5f9-3ba3b7072e76@alien>
  1 sibling, 1 reply; 3+ messages in thread
From: Clem Cole @ 2021-11-30 16:47 UTC (permalink / raw)
  To: COFF


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Moving to COFF as this is less UNIX and more computer architecture and
design style...

On Tue, Nov 30, 2021 at 3:07 AM <pbirkel@gmail.com> wrote:

> Given a random logic design it's efficient to organize the ISA encoding
> to maximize its regularity.

Probably also of some benefit to compilers in a memory-constrained
> environment?
>
To be honest, I think that the regularity of the instruction set is less
for the logic and more for the compiler.  Around the time the 11 was being
created Bill Wulf and I think Gordan as co-author, wrote a paper about how
instruction set design, the regularity, lack of special cases, made it
easier to write a code optimizer.  Remember a couple of former Bell and
Wulf students were heavily involved in the 11 (Strecker being the main one
I can think of off the top of my head).

Also remember that Gordan and the CMU types of those days were beginning to
create what we now call Hardware Description Languages (HDL).  Gordon
describes in "Bell and Newell" (the definitive Computer Structures book of
the 1970s) his Processor-Memory-Switch (PMS) diagrams.   The original 11
(which would become the 11/20) was first described as a set of PMS
diagrams.   PMS of course, beget the Instruction Set Processor Language
(ISPL) that Mario created a couple of years later.   While ISPL was after
the 11 had been designed, ISPL could synthesize a system using PDP-16 RTM
modules.  A later version from our old friend from UNIX land, Ted Kowalski
[his PhD thesis actually], that could spit out TTL from the later ISPS
simulator and compiler [the S being simulation].   ISPS would beget VHDL,
which beget today Verilog/System Verilog.

IIRC it was a lecture Gordon Gordan gave us WRT to microcode *vs.* direct
logic.  He offered that microcode had the advantage that you could more
easily update things in the field, but he also felt that if we could catch
the errors before you released the HW to the world, and if we could then
directly synthesize, that would be even better - no errors/no need to
update.   That said, by the 11/40, DEC started to microcode the 11's,
although as you point out the 11/34 and later 11/44, where more direct
logic than the 11/40 - and of course Wulf would created the 11/40e - which
writeable control store so they add some instructions and eventually build
C.mmp.

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* Re: [COFF] Encoding an ISA: Random Logic vs. Control Stores
  2021-11-30 16:47 ` [COFF] Encoding an ISA: Random Logic vs. Control Stores Clem Cole
@ 2021-11-30 19:04   ` Bakul Shah
  0 siblings, 0 replies; 3+ messages in thread
From: Bakul Shah @ 2021-11-30 19:04 UTC (permalink / raw)
  To: Clem Cole; +Cc: COFF


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On Nov 30, 2021, at 8:49 AM, Clem Cole <clemc@ccc.com> wrote:
> 
> Also remember that Gordan and the CMU types of those days were beginning to create what we now call Hardware Description Languages (HDL).  Gordon describes in "Bell and Newell" (the definitive Computer Structures book of the 1970s) his Processor-Memory-Switch (PMS) diagrams.   The original 11 (which would become the 11/20) was first described as a set of PMS diagrams.   PMS of course, beget the Instruction Set Processor Language (ISPL) that Mario created a couple of years later.   While ISPL was after the 11 had been designed, ISPL could synthesize a system using PDP-16 RTM modules.  A later version from our old friend from UNIX land, Ted Kowalski [his PhD thesis actually], that could spit out TTL from the later ISPS simulator and compiler [the S being simulation].   ISPS would beget VHDL, which beget today Verilog/System Verilog.

Verilog has no direct connection with VHDL. Phil Moorby had been working with HILO simulators since 1976 so had considerable experience with simulators and based on that experience he designed Verilog as a fast gate & switch level simulator, as well as for synthesis.
See https://community.cadence.com/cadence_blogs_8/b/ii/posts/q-amp-a-phil-moorby-hdl-pioneer-and-cadence-fellow-from-verilog-to-parallel-programming and https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/phil-moorby

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* Re: [COFF] [TUHS] Encoding an ISA
       [not found]                 ` <CAP6exY+i9ZMyJOd2zWXUDnLA21SFig+gbSVFbfGdU9F1Tz3bUg@mail.gmail.com>
@ 2021-12-01 21:56                   ` Warren Toomey
  0 siblings, 0 replies; 3+ messages in thread
From: Warren Toomey @ 2021-12-01 21:56 UTC (permalink / raw)
  Cc: TUHS main list

All, I think it's time to move the ISA and random logic threads over to COFF :-)

Thanks!
	Warren
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