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[107.215.223.229]) by smtp.gmail.com with ESMTPSA id y16sm9795800qki.41.2021.11.30.11.10.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Nov 2021 11:10:11 -0800 (PST) From: Bakul Shah Mime-Version: 1.0 (1.0) Date: Tue, 30 Nov 2021 11:04:25 -0800 Message-Id: <677CBEE9-8651-4587-8F38-238107939720@iitbombay.org> References: In-Reply-To: To: Clem Cole X-Mailer: iPad Mail (19B74) Subject: Re: [COFF] Encoding an ISA: Random Logic vs. Control Stores X-BeenThere: coff@minnie.tuhs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Computer Old Farts Forum List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: COFF Content-Type: multipart/mixed; boundary="===============5978546473039346394==" Errors-To: coff-bounces@minnie.tuhs.org Sender: "COFF" --===============5978546473039346394== Content-Type: multipart/alternative; boundary=Apple-Mail-73D4D5E9-96ED-4C7E-80E7-C3D3538B7DB4 Content-Transfer-Encoding: 7bit --Apple-Mail-73D4D5E9-96ED-4C7E-80E7-C3D3538B7DB4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable On Nov 30, 2021, at 8:49 AM, Clem Cole wrote: >=20 > Also remember that Gordan and the CMU types of those days were beginning t= o create what we now call Hardware Description Languages (HDL). Gordon desc= ribes in "Bell and Newell" (the definitive Computer Structures book of the 1= 970s) his Processor-Memory-Switch (PMS) diagrams. The original 11 (which w= ould become the 11/20) was first described as a set of PMS diagrams. PMS o= f course, beget the Instruction Set Processor Language (ISPL) that Mario cre= ated a couple of years later. While ISPL was after the 11 had been designe= d, ISPL could synthesize a system using PDP-16 RTM modules. A later version= from our old friend from UNIX land, Ted Kowalski [his PhD thesis actually],= that could spit out TTL from the later ISPS simulator and compiler [the S b= eing simulation]. ISPS would beget VHDL, which beget today Verilog/System V= erilog. Verilog has no direct connection with VHDL. Phil Moorby had been working wit= h HILO simulators since 1976 so had considerable experience with simulators a= nd based on that experience he designed Verilog as a fast gate & switch leve= l simulator, as well as for synthesis. See https://community.cadence.com/cadence_blogs_8/b/ii/posts/q-amp-a-phil-mo= orby-hdl-pioneer-and-cadence-fellow-from-verilog-to-parallel-programming and= https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/phil-= moorby= --Apple-Mail-73D4D5E9-96ED-4C7E-80E7-C3D3538B7DB4 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable
On N= ov 30, 2021, at 8:49 AM, Clem Cole <clemc@ccc.com> wrote:

=
Also rememb= er that Gordan and the CMU types of those days were beginning to create what= we now call Hardware Description Languages (HDL).  Gordon describes in= "Bell and Newell" (the definitive Computer Structures book of the 1970s) hi= s Processor-Memory-Switch (PMS) diagrams.   The original 11 (which woul= d become the 11/20) was first described as a set of PMS diagrams.   PMS= of course, beget the Instruction Set Processor Language (ISPL) that Mario c= reated a couple of years later.   While ISPL was after the 11 had b= een designed, ISPL could synthesize a system using PDP-16 RTM modules. = A later version from our old friend from UNIX land, Ted Kowalski [his PhD t= hesis actually], that could spit out TTL from the later ISPS simulator a= nd compiler [the S being simulation].   ISPS would beget VHDL, which be= get today Verilog/System Verilog.

Verilog has no direct connection with VHDL. Phil Moorby had been w= orking with HILO simulators since 1976 so had considerable experience with s= imulators and based on that experience he designed Verilog as a fast gate &a= mp; switch level simulator, as well as for synthesis.
= --Apple-Mail-73D4D5E9-96ED-4C7E-80E7-C3D3538B7DB4-- --===============5978546473039346394== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KQ09GRiBtYWls aW5nIGxpc3QKQ09GRkBtaW5uaWUudHVocy5vcmcKaHR0cHM6Ly9taW5uaWUudHVocy5vcmcvY2dp LWJpbi9tYWlsbWFuL2xpc3RpbmZvL2NvZmYK --===============5978546473039346394==--