From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 28005 invoked from network); 21 Sep 2020 14:10:32 -0000 Received: from mother.openwall.net (195.42.179.200) by inbox.vuxu.org with ESMTPUTF8; 21 Sep 2020 14:10:32 -0000 Received: (qmail 32766 invoked by uid 550); 21 Sep 2020 14:10:25 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 32733 invoked from network); 21 Sep 2020 14:10:23 -0000 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1600697425; h=Content-Transfer-Encoding: Content-Type: MIME-Version: Message-ID: Date: Subject: In-Reply-To: References: Cc: To: From: Sender; bh=XPZ9x9UcCTV78zHsLKfTEwDjNi/OCtC/h7/ISvqJSLo=; b=vX70zpOxMuwPuKCA70FOQ8hT0XdSDKtcCNvckISUpWJgoaajOJH0+iR0q/lw8agVsqHIFl2w /zjFCohWoLA1GcSr0eQ4kkdu8SvYxHfEDR4s2aPv1KzTFUd81Tss9qqbwDh+1vMOqWfLYyaS vESHYQ4gURWyNmenQhuxAc2D8Po= X-Mailgun-Sending-Ip: 104.130.96.5 X-Mailgun-Sid: WyI1MGQzMyIsICJtdXNsQGxpc3RzLm9wZW53YWxsLmNvbSIsICJiZTllNGEiXQ== Sender: sidneym=codeaurora.org@mg.codeaurora.org DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B617BC433C8 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sidneym@codeaurora.org From: To: "'Rich Felker'" Cc: References: <20200619224624.GO6430@brightrain.aerifal.cx> <0a7201d646aa$921b84f0$b6528ed0$@codeaurora.org> <20200620032032.GR6430@brightrain.aerifal.cx> <078f01d65edc$80e892f0$82b9b8d0$@codeaurora.org> <20200723215603.GA755469@port70.net> <110801d68c6a$dfe3f950$9fabebf0$@codeaurora.org> <20200917013236.GV3265@brightrain.aerifal.cx> <073501d68d42$4a8c6080$dfa52180$@codeaurora.org> <20200918010806.GX3265@brightrain.aerifal.cx> <025a01d68f4f$bd211aa0$37634fe0$@codeaurora.org> <20200920171707.GC3265@brightrain.aerifal.cx> In-Reply-To: <20200920171707.GC3265@brightrain.aerifal.cx> Date: Mon, 21 Sep 2020 09:09:27 -0500 Message-ID: <05b901d69020$d1f44c50$75dce4f0$@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQGgt9+emke+h51JY8OqgloCJAFSoAKKfuZmAh2x56MC/BF0FgHdLCtsAfpQWqICdr3uKwGAdZcBApvSbHACxGc6KQK3zh+CqSJlrPA= Content-Language: en-us Subject: RE: [musl] Hexagon DSP support > -----Original Message----- > From: 'Rich Felker' > Sent: Sunday, September 20, 2020 12:17 PM > To: sidneym@codeaurora.org > Cc: musl@lists.openwall.com > Subject: Re: [musl] Hexagon DSP support > > On Sun, Sep 20, 2020 at 08:12:47AM -0500, sidneym@codeaurora.org wrote: > > > > > > [...] > > > > > > +#define a_barrier a_barrier > > > > > > +static inline void a_barrier() { > > > > > > + __asm__ __volatile__ ("barrier" ::: "memory"); } > > > > > > > > > > Is the barrier implied in memw_locked? If not, there need to be > > > > > explicit barriers in all the atomic functions. > > > > > > > > Yes, if there is any memory access on the reserved address the > > > > reservation is lost and the predicate is false. > > > > > > That's not what a barrier means. The question is whether it orders > > > all > > access > > > to *other* memory, not the address with the reservation on it. > > > In other words, musl's a_*() atomics need to be full seq_cst model > > > operations, not relaxed atomics. > > > > Per our spec: > > "Threads in the Hexagon processor follow a sequentially consistent > > memory model at a packet granularity. Threads interleave their memory > > operations with one another in an arbitrary but fair manner. This > > results in a consistent program order that is globally observable by > > all threads in the same order." > > Can you clarify or provide a reference for what 'packet granularity' > means? If there's actually a full builtin seq_cst order I don't see what the > barrier instruction exists for to begin with. > Packet granularity is like instruction granularity, every operation within the packet happens in parallel. There is an exception since packets can have dual stores. They happen in a prescribed order. A packet has 4 slots but dual stores must be in slots 0 & 1. Stores in slot 1 happen before stores in slot 0. Slot 0 is the highest address in the packet so the store order would appear as it would if you disassembled the code. barrier is used for thread-to-external-memory. All observers in the "global shared domain" would see the store after the barrier finished. "For devices external to the Hexagon processor, the processor follows a weakly-ordered memory model. Explicit synchronization is required to ensure order between memory accesses." > Rich