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| | .global ___setjmp
.hidden ___setjmp
.global __setjmp
.global _setjmp
.global setjmp
.type __setjmp,@function
.type _setjmp,@function
.type setjmp,@function
___setjmp:
__setjmp:
_setjmp:
setjmp:
# 0) store IP into 0, then into the jmpbuf pointed to by r3 (first arg)
mflr 0
std 0, 0*8(3)
# 1) store cr
mfcr 0
std 0, 1*8(3)
# 2) store r1-r2 (SP and TOC)
std 1, 2*8(3)
std 2, 3*8(3)
# 3) store r14-31
std 14, 4*8(3)
std 15, 5*8(3)
std 16, 6*8(3)
std 17, 7*8(3)
std 18, 8*8(3)
std 19, 9*8(3)
std 20, 10*8(3)
std 21, 11*8(3)
std 22, 12*8(3)
std 23, 13*8(3)
std 24, 14*8(3)
std 25, 15*8(3)
std 26, 16*8(3)
std 27, 17*8(3)
std 28, 18*8(3)
std 29, 19*8(3)
std 30, 20*8(3)
std 31, 21*8(3)
# 4) store floating point registers f14-f31
stfd 14, 22*8(3)
stfd 15, 23*8(3)
stfd 16, 24*8(3)
stfd 17, 25*8(3)
stfd 18, 26*8(3)
stfd 19, 27*8(3)
stfd 20, 28*8(3)
stfd 21, 29*8(3)
stfd 22, 30*8(3)
stfd 23, 31*8(3)
stfd 24, 32*8(3)
stfd 25, 33*8(3)
stfd 26, 34*8(3)
stfd 27, 35*8(3)
stfd 28, 36*8(3)
stfd 29, 37*8(3)
stfd 30, 38*8(3)
stfd 31, 39*8(3)
# 5) store vector registers v20-v31
addi 3, 3, 40*8
lvx 1, 0, 3
#if __BIG_ENDIAN__
lvsr 0, 0, 3
vperm 1, 1, 1, 0
vperm 2, 1, 20, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 20, 21, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 21, 22, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 22, 23, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 23, 24, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 24, 25, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 25, 26, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 26, 27, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 27, 28, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 28, 29, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 29, 30, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 30, 31, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 31, 31, 0 ; stvx 2, 0, 3
#else
lvsl 0, 0, 3
vperm 1, 1, 1, 0
vperm 2, 20, 1, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 21, 20, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 22, 21, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 23, 22, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 24, 23, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 25, 24, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 26, 25, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 27, 26, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 28, 27, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 29, 28, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 30, 29, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 31, 30, 0 ; stvx 2, 0, 3 ; addi 3, 3, 16
vperm 2, 31, 31, 0 ; stvx 2, 0, 3
#endif
# 6) return 0
li 3, 0
blr
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