From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/10128 Path: news.gmane.org!not-for-mail From: "Zhao, Weiming" Newsgroups: gmane.linux.lib.musl.general Subject: Re: build musl for armv7m Date: Tue, 14 Jun 2016 10:40:54 -0700 Message-ID: <0e13c593-33fa-be67-5e73-cec7d7edfe15@codeaurora.org> References: <805971fb5f9b1ee12edab9b7f3e86114@codeaurora.org> <20160614130036.GD10893@brightrain.aerifal.cx> <4858c023-2689-cec7-5335-15c33b8c8b92@codeaurora.org> <20160614163252.GQ22574@port70.net> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------229B7B273FF2EA3B30774730" X-Trace: ger.gmane.org 1465926085 29266 80.91.229.3 (14 Jun 2016 17:41:25 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Tue, 14 Jun 2016 17:41:25 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-10141-gllmg-musl=m.gmane.org@lists.openwall.com Tue Jun 14 19:41:12 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1bCsKt-0007Dk-HU for gllmg-musl@m.gmane.org; Tue, 14 Jun 2016 19:41:11 +0200 Original-Received: (qmail 22040 invoked by uid 550); 14 Jun 2016 17:41:08 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 22015 invoked from network); 14 Jun 2016 17:41:07 -0000 X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham autolearn_force=no version=3.4.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: Xref: news.gmane.org gmane.linux.lib.musl.general:10128 Archived-At: This is a multi-part message in MIME format. --------------229B7B273FF2EA3B30774730 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Please review the changes. I'm able to build libc.a with -mcpu=cortex-m3 -Wa,-implicit-it=always using clang + gas Thanks, weiming On 6/14/2016 9:58 AM, Zhao, Weiming wrote: > Thank you, Szabolcs. > > It's GAS-only flag, clang's integrated-as doesn't support it. I can > use -no-integrated-as. > > It also expose other errors: > > src/thread/arm/atomics.s:9: Error: cannot use register index with > PC-relative addressing -- `ldr ip,[pc,ip]' > > Clang's integrated-as accepts it but seems encoded incorrectly. > > I can fix it. > > > On 6/14/2016 9:32 AM, Szabolcs Nagy wrote: >> * Zhao, Weiming [2016-06-14 09:12:17 -0700]: >>> I haven't did a full test as the functions I modified are not >>> actually being >>> used. >>> >>> It is a bare-metal environment, using clang to compile. >>> >>> Main flags are -mcpu=cortex-m3 -Os -fdata-sections -ffunction-sections >>> -mno-unaligned-access >>> >>> Could you please let me know the gas option? >>> >> -mimplicit-it=always >> >> https://sourceware.org/binutils/docs/as/ARM-Options.html >> >>> Thanks, >>> >>> Weiing >>> >>> On 6/14/2016 6:00 AM, Rich Felker wrote: >>>> On Tue, Jun 14, 2016 at 01:49:40AM -0700, weimingz@codeaurora.org >>>> wrote: >>>>> Hi, >>>>> >>>>> I'm building MUSL with -mcpu=cortex-m3. There are a few .s files >>>>> that cannot be assembled because: (1) use predicated instructions >>>>> without IT instr (2) use sp inside reg list in ldmia/stmia. >>>>> >>>>> Please help to review the attached patch. >>>> Did you test anything? These patches do not result in working code; >>>> they just make it assemble without errors. There's already a gas >>>> option to automatically add IT instructions where needed for >>>> thumb-only targets, but that's not the only thing needed to support >>>> thumb-only/cortex-m. I'd be interested in knowing more about the setup >>>> you're trying to target. Is it Linux or bare-metal? If Linux, are you >>>> going to use the ARM/FDPIC toolchain & kernel mods? I'm about to leave >>>> at the moment but I'll follow up with a more detailed review of your >>>> patch later. >>>> >>>>> Also, is there any easy way of disabling string/arm/memcpy_le.S ? >>>>> For baremetal, unaligned access may be unavailable. >>>> That file does not perform any unaligned access. It should work on any >>>> EABI-supported version of the arm instruction set. >>>> >>>> Rich >>> -- >>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >>> hosted by The Linux Foundation > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation --------------229B7B273FF2EA3B30774730 Content-Type: text/plain; charset=UTF-8; name="cortex_m3.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="cortex_m3.patch" diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s index e28d8f3..e9b9b32 100644 --- a/src/setjmp/arm/longjmp.s +++ b/src/setjmp/arm/longjmp.s @@ -8,7 +8,9 @@ longjmp: mov ip,r0 movs r0,r1 moveq r0,#1 - ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} + ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp} + ldr sp, [ip]! + ldr lr, [ip]! adr r1,1f ldr r2,1f diff --git a/src/setjmp/arm/setjmp.s b/src/setjmp/arm/setjmp.s index 8779163..fd380b0 100644 --- a/src/setjmp/arm/setjmp.s +++ b/src/setjmp/arm/setjmp.s @@ -9,7 +9,9 @@ __setjmp: _setjmp: setjmp: mov ip,r0 - stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} + stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp} + str sp, [ip]! + str lr, [ip]! mov r0,#0 adr r1,1f diff --git a/src/string/arm/memcpy_le.S b/src/string/arm/memcpy_le.S index 4db4844..2517d15 100644 --- a/src/string/arm/memcpy_le.S +++ b/src/string/arm/memcpy_le.S @@ -241,7 +241,8 @@ non_congruent: beq 2f ldr r5, [r1], #4 sub r2, r2, #4 - orr r4, r3, r5, lsl lr + lsl r4, r5, lr + orr r4, r3, r4 mov r3, r5, lsr r12 str r4, [r0], #4 cmp r2, #4 @@ -348,7 +349,8 @@ less_than_thirtytwo: 1: ldr r5, [r1], #4 sub r2, r2, #4 - orr r4, r3, r5, lsl lr + lsl r4, r5, lr + orr r4, r3, r4 mov r3, r5, lsr r12 str r4, [r0], #4 cmp r2, #4 diff --git a/src/thread/arm/atomics.s b/src/thread/arm/atomics.s index 673fc03..a4bd03a 100644 --- a/src/thread/arm/atomics.s +++ b/src/thread/arm/atomics.s @@ -6,7 +6,8 @@ .type __a_barrier,%function __a_barrier: ldr ip,1f - ldr ip,[pc,ip] + add ip,pc,ip + ldr ip,[ip] add pc,pc,ip 1: .word __a_barrier_ptr-1b .global __a_barrier_dummy @@ -40,7 +41,8 @@ __a_barrier_v7: .type __a_cas,%function __a_cas: ldr ip,1f - ldr ip,[pc,ip] + add ip,pc,ip + ldr ip,[ip] add pc,pc,ip 1: .word __a_cas_ptr-1b .global __a_cas_dummy @@ -85,7 +87,8 @@ __aeabi_read_tp: .type __a_gettp,%function __a_gettp: ldr r0,1f - ldr r0,[pc,r0] + add r0,pc,r0 + ldr r0,[r0] add pc,pc,r0 1: .word __a_gettp_ptr-1b .global __a_gettp_dummy --------------229B7B273FF2EA3B30774730--