From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/12201 Path: news.gmane.org!.POSTED!not-for-mail From: Andre McCurdy Newsgroups: gmane.linux.lib.musl.general Subject: [PATCH] remove a_ctz_l from atomic_arch.h Date: Mon, 4 Dec 2017 18:05:21 -0800 Message-ID: <1512439521-12466-1-git-send-email-armccurdy@gmail.com> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org X-Trace: blaine.gmane.org 1512439548 25121 195.159.176.226 (5 Dec 2017 02:05:48 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Tue, 5 Dec 2017 02:05:48 +0000 (UTC) Cc: Andre McCurdy To: musl@lists.openwall.com Original-X-From: musl-return-12217-gllmg-musl=m.gmane.org@lists.openwall.com Tue Dec 05 03:05:44 2017 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1eM2cC-0006Ie-BP for gllmg-musl@m.gmane.org; Tue, 05 Dec 2017 03:05:44 +0100 Original-Received: (qmail 32680 invoked by uid 550); 5 Dec 2017 02:05:42 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 32645 invoked from network); 5 Dec 2017 02:05:42 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=Qf9uK+NMH7rB3RW+aIDR1ql/Jp7KF734P3y3/OfEuDg=; b=SW+ldidZ8vqtGTMlkYsaNS3qD/npbfDMx6ZiDs28EY6iEJqu3ZtkEI7KsLasES9Yql +guZpiJd+dBN95lbS2weHdNh/0J3QWzVNNtVwHoXeh32HsRznPNOhULuroZFC/Ww7Pdq 23SwQCrF4Czt2NokmSRILc0Szbx4NI4XnJ4/ZJOkwB55tKy+OSwCPfS041zEXajKSGC0 RD9dGVuNVmZqNP/7SMK033crsTKA6f7JPcaolf3fCtGM68Y4qCgnYxMew1rSoxaND3CK XBMcF0zPki5A5W5FL/SpcVp43oH2ZFAFy7Lg5Yun7TfbE8IrRTMsJAA1Rdv/9wNWTCOM v2EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Qf9uK+NMH7rB3RW+aIDR1ql/Jp7KF734P3y3/OfEuDg=; b=aNny0ic7l9s7EvD0U0aZGE/gO3kVRz2/D4AJ4vfzyRwPQfFcaA+pMS74KLXGcfsvav 9wBq+jJnPKoHIcMl6+i6rBzSDyAaJaCyMvQJt19hUcVdrGnG6sDz9oq/QV9VaXtLSMnm IL4lEKmNPvb76j/A/BdpDa6ul34ppqg96drlCG8f7JfiRw/U1g4giJbAwGnWc3hC43Sb HyI88HtusK2VSWfz2Op52CtgiKZeZfO9/brj6cTHpXMbUEW31EbNuLMjxsksyDTo1S4H QMDZEr+TWbcLdg55ItScM6R3r6hGOdm/H327DfAWo4NYzZOUv/h8wyt5SYcxRzXg+kBg ggKQ== X-Gm-Message-State: AJaThX7AkTkzArpI3Ggw6iINIQMe4SDrYRvFTjXB6caifHpKQqriVfNk ikBZEw///mGuV21ax3pRCm5HNg== X-Google-Smtp-Source: AGs4zMaPVnpZ10brqxuT8NkJ9lV2u1b6lWudeCJCXunF+OtPtH72xiS6MF09GEVRBkWv2HRkYMwy3A== X-Received: by 10.157.91.11 with SMTP id x11mr18132868oth.161.1512439529871; Mon, 04 Dec 2017 18:05:29 -0800 (PST) X-Mailer: git-send-email 1.9.1 Xref: news.gmane.org gmane.linux.lib.musl.general:12201 Archived-At: Arch specific code should now define only a_ctz_32 and/or a_ctz_64 and a_ctz_l will always be defined generically. Provide an ARM specific a_ctz_32 helper function for ARM architecture versions for which it can be implemented efficiently via the "rbit" instruction (ie all Thumb-2 capable versions of ARM v6 and above). Provide a more optimal generic a_ctz_32 for targets which support a_clz_32 but not a_ctz_32 (e.g. ARMv5) and define generic a_ctz_64 in terms of a_ctz_32 to make better use of architure specific a_ctz_32. Signed-off-by: Andre McCurdy --- arch/arm/atomic_arch.h | 12 ++++++++++++ arch/i386/atomic_arch.h | 6 +++--- arch/x32/atomic_arch.h | 4 ++-- src/internal/atomic.h | 42 +++++++++++++++++++++++------------------- 4 files changed, 40 insertions(+), 24 deletions(-) diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h index 6e2e3b4..62458b4 100644 --- a/arch/arm/atomic_arch.h +++ b/arch/arm/atomic_arch.h @@ -91,4 +91,16 @@ static inline int a_clz_32(uint32_t x) return x; } +#if __ARM_ARCH_6T2__ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7 + +#define a_ctz_32 a_ctz_32 +static inline int a_ctz_32(uint32_t x) +{ + uint32_t xr; + __asm__ ("rbit %0, %1" : "=r"(xr) : "r"(x)); + return a_clz_32(xr); +} + +#endif + #endif diff --git a/arch/i386/atomic_arch.h b/arch/i386/atomic_arch.h index 7d2a48a..047fb68 100644 --- a/arch/i386/atomic_arch.h +++ b/arch/i386/atomic_arch.h @@ -92,10 +92,10 @@ static inline int a_ctz_64(uint64_t x) return r; } -#define a_ctz_l a_ctz_l -static inline int a_ctz_l(unsigned long x) +#define a_ctz_32 a_ctz_32 +static inline int a_ctz_32(uint32_t x) { - long r; + int r; __asm__( "bsf %1,%0" : "=r"(r) : "r"(x) ); return r; } diff --git a/arch/x32/atomic_arch.h b/arch/x32/atomic_arch.h index a744c29..918c2d4 100644 --- a/arch/x32/atomic_arch.h +++ b/arch/x32/atomic_arch.h @@ -106,8 +106,8 @@ static inline int a_ctz_64(uint64_t x) return x; } -#define a_ctz_l a_ctz_l -static inline int a_ctz_l(unsigned long x) +#define a_ctz_32 a_ctz_32 +static inline int a_ctz_32(uint32_t x) { __asm__( "bsf %1,%0" : "=r"(x) : "r"(x) ); return x; diff --git a/src/internal/atomic.h b/src/internal/atomic.h index ab473dd..f938879 100644 --- a/src/internal/atomic.h +++ b/src/internal/atomic.h @@ -251,6 +251,22 @@ static inline void a_crash() } #endif +#ifndef a_ctz_32 +#define a_ctz_32 a_ctz_32 +static inline int a_ctz_32(uint32_t x) +{ +#ifdef a_clz_32 + return 31-a_clz_32(x&-x); +#else + static const char debruijn32[32] = { + 0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13, + 31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14 + }; + return debruijn32[(x&-x)*0x076be629 >> 27]; +#endif +} +#endif + #ifndef a_ctz_64 #define a_ctz_64 a_ctz_64 static inline int a_ctz_64(uint64_t x) @@ -261,22 +277,23 @@ static inline int a_ctz_64(uint64_t x) 63, 52, 6, 26, 37, 40, 33, 47, 61, 45, 43, 21, 23, 58, 17, 10, 51, 25, 36, 32, 60, 20, 57, 16, 50, 31, 19, 15, 30, 14, 13, 12 }; - static const char debruijn32[32] = { - 0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13, - 31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14 - }; if (sizeof(long) < 8) { uint32_t y = x; if (!y) { y = x>>32; - return 32 + debruijn32[(y&-y)*0x076be629 >> 27]; + return 32 + a_ctz_32(y); } - return debruijn32[(y&-y)*0x076be629 >> 27]; + return a_ctz_32(y); } return debruijn64[(x&-x)*0x022fdd63cc95386dull >> 58]; } #endif +static inline int a_ctz_l(unsigned long x) +{ + return (sizeof(long) < 8) ? a_ctz_32(x) : a_ctz_64(x); +} + #ifndef a_clz_64 #define a_clz_64 a_clz_64 static inline int a_clz_64(uint64_t x) @@ -298,17 +315,4 @@ static inline int a_clz_64(uint64_t x) } #endif -#ifndef a_ctz_l -#define a_ctz_l a_ctz_l -static inline int a_ctz_l(unsigned long x) -{ - static const char debruijn32[32] = { - 0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13, - 31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14 - }; - if (sizeof(long) == 8) return a_ctz_64(x); - return debruijn32[(x&-x)*0x076be629 >> 27]; -} -#endif - #endif -- 1.9.1