From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.4 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: (qmail 11104 invoked from network); 16 Apr 2020 00:17:35 -0000 Received-SPF: pass (mother.openwall.net: domain of lists.openwall.com designates 195.42.179.200 as permitted sender) receiver=inbox.vuxu.org; client-ip=195.42.179.200 envelope-from= Received: from mother.openwall.net (195.42.179.200) by inbox.vuxu.org with UTF8ESMTPZ; 16 Apr 2020 00:17:35 -0000 Received: (qmail 16303 invoked by uid 550); 16 Apr 2020 00:17:33 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 16285 invoked from network); 16 Apr 2020 00:17:32 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:subject:to:cc:references:in-reply-to:mime-version :message-id:content-transfer-encoding; bh=y+BJV5qqgRb7VaqgWi198OzXB7Ja/Atr9zrjQtiZUt8=; b=VrzWL1OUAF2ebv9iSydARa4PXImyr0+Ogc15W/pl/d/36kWXCIw5DfVX2Vi2WAf9wH +zesKlDaY5bDvEAYiXNmbp9G9DVkqYNqpuLtmzjwjZxMEfG909Vv3/VrnObHPl7+bIbq N16TsZIsNNMFpP+km9bV/DuTbC7oYRZ5pEjO+IGZxNJxiq9TOb7+UTQHisngBlexygqU OQpDiWW3wFoLENBjQ9+GrQeu3nRkdHBsEU2CxsO+KWtc4vvOJAFA1HAIiCX4bH6J2K5n y8aHzfGJNYkSyTdBo7ikGkEcPxXGbMYOP2JT5SDU96gBF1hu11NK1eJ+CYa9MoIPwxwP T6Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:subject:to:cc:references:in-reply-to :mime-version:message-id:content-transfer-encoding; bh=y+BJV5qqgRb7VaqgWi198OzXB7Ja/Atr9zrjQtiZUt8=; b=fmRKZDiwq32USmL4dkl/Xqddz1w0MeRZWgxX26iJ6MIcLoG2SAyAydP/P3oaeSHwoM PDVJIqdD4/J9qimQ4/s/W5/bVm7Wt4rDdwKPRdDgf6FSdub9k8ng9GqhzUQAe2AsFuxO /1cpk9Hqgd171+FEStybtwYAyoGKbF1au+rljKSTrg/YZBgZwc5+SNeDMCGOaQ04+3yA hZEmSlnyj6J3SXg8nXC+trSNMvu8dlassTvi+hyd2J1/nj1bxGSOUKrES0jF/zeNMEvM RTD7tS+GN6euYTo0jo+YxdMXiM34Un9AFbVCzWqhJ4kBGUnzq7Cn65S1cMzRCDGC7QKu Iv9w== X-Gm-Message-State: AGi0PuZb0Ih9OEafHxXvx95KAuABPydpC3Aw8DEIiyt3DqswZPICLRj5 aCeUWEcn2pVcFa7QWKza10+0mO6U X-Google-Smtp-Source: APiQypJos/oiTEISlrLmmjfEAkwnh+wjbdsgv1Plq5zBTpjVYPc6zgVrBHTLnpEuHT6HypuV+nSQzg== X-Received: by 2002:a63:6d4a:: with SMTP id i71mr29090931pgc.445.1586996240446; Wed, 15 Apr 2020 17:17:20 -0700 (PDT) Date: Thu, 16 Apr 2020 10:16:54 +1000 From: Nicholas Piggin To: Rich Felker Cc: libc-alpha@sourceware.org, libc-dev@lists.llvm.org, linuxppc-dev@lists.ozlabs.org, musl@lists.openwall.com, Segher Boessenkool References: <1586931450.ub4c8cq8dj.astroid@bobo.none> <20200415225539.GL11469@brightrain.aerifal.cx> In-Reply-To: <20200415225539.GL11469@brightrain.aerifal.cx> MIME-Version: 1.0 Message-Id: <1586994952.nnxigedbu2.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [musl] Powerpc Linux 'scv' system call ABI proposal take 2 Excerpts from Rich Felker's message of April 16, 2020 8:55 am: > On Thu, Apr 16, 2020 at 07:45:09AM +1000, Nicholas Piggin wrote: >> I would like to enable Linux support for the powerpc 'scv' instruction, >> as a faster system call instruction. >>=20 >> This requires two things to be defined: Firstly a way to advertise to=20 >> userspace that kernel supports scv, and a way to allocate and advertise >> support for individual scv vectors. Secondly, a calling convention ABI >> for this new instruction. >>=20 >> Thanks to those who commented last time, since then I have removed my >> answered questions and unpopular alternatives but you can find them >> here >>=20 >> https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-January/203545.html >>=20 >> Let me try one more with a wider cc list, and then we'll get something >> merged. Any questions or counter-opinions are welcome. >>=20 >> System Call Vectored (scv) ABI >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D >>=20 >> The scv instruction is introduced with POWER9 / ISA3, it comes with an >> rfscv counter-part. The benefit of these instructions is performance >> (trading slower SRR0/1 with faster LR/CTR registers, and entering the >> kernel with MSR[EE] and MSR[RI] left enabled, which can reduce MSR=20 >> updates. The scv instruction has 128 interrupt entry points (not enough=20 >> to cover the Linux system call space). >>=20 >> The proposal is to assign scv numbers very conservatively and allocate=20 >> them as individual HWCAP features as we add support for more. The zero=20 >> vector ('scv 0') will be used for normal system calls, equivalent to 'sc= '. >>=20 >> Advertisement >>=20 >> Linux has not enabled FSCR[SCV] yet, so the instruction will cause a >> SIGILL in current environments. Linux has defined a HWCAP2 bit=20 >> PPC_FEATURE2_SCV for SCV support, but does not set it. >>=20 >> When scv instruction support and the scv 0 vector for system calls are=20 >> added, PPC_FEATURE2_SCV will indicate support for these. Other vectors=20 >> should not be used without future HWCAP bits indicating support, which i= s >> how we will allocate them. (Should unallocated ones generate SIGILL, or >> return -ENOSYS in r3?) >>=20 >> Calling convention >>=20 >> The proposal is for scv 0 to provide the standard Linux system call ABI=20 >> with the following differences from sc convention[1]: >>=20 >> - LR is to be volatile across scv calls. This is necessary because the=20 >> scv instruction clobbers LR. From previous discussion, this should be=20 >> possible to deal with in GCC clobbers and CFI. >>=20 >> - CR1 and CR5-CR7 are volatile. This matches the C ABI and would allow t= he >> kernel system call exit to avoid restoring the CR register (although=20 >> we probably still would anyway to avoid information leak). >>=20 >> - Error handling: I think the consensus has been to move to using negati= ve >> return value in r3 rather than CR0[SO]=3D1 to indicate error, which ma= tches >> most other architectures and is closer to a function call. >>=20 >> The number of scratch registers (r9-r12) at kernel entry seems=20 >> sufficient that we don't have any costly spilling, patch is here[2]. =20 >>=20 >> [1] https://github.com/torvalds/linux/blob/master/Documentation/powerpc/= syscall64-abi.rst >> [2] https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-February/204840= .html >=20 > My preference would be that it work just like the i386 AT_SYSINFO > where you just replace "int $128" with "call *%%gs:16" and the kernel > provides a stub in the vdso that performs either scv or the old > mechanism with the same calling convention. Then if the kernel doesn't > provide it (because the kernel is too old) libc would have to provide > its own stub that uses the legacy method and matches the calling > convention of the one the kernel is expected to provide. I'm not sure if that's necessary. That's done on x86-32 because they select different sequences to use based on the CPU running and if the host kernel is 32 or 64 bit. Sure they could in theory have a bunch of HWCAP bits and select the right sequence in libc as well I suppose. > Note that any libc that actually makes use of the new functionality is > not going to be able to make clobbers conditional on support for it; > branching around different clobbers is going to defeat any gains vs > always just treating anything clobbered by either method as clobbered. Well it would have to test HWCAP and patch in or branch to two=20 completely different sequences including register save/restores yes. You could have the same asm and matching clobbers to put the sequence inline and then you could patch the one sc/scv instruction I suppose. A bit of logic to select between them doesn't defeat gains though, it's about 90 cycle improvement which is a handful of branch mispredicts=20 so it really is an improvement. Eventually userspace will stop=20 supporting the old variant too. > Likewise, it's not useful to have different error return mechanisms > because the caller just has to branch to support both (or the > kernel-provided stub just has to emulate one for it; that could work > if you really want to change the bad existing convention). >=20 > Thoughts? The existing convention has to change somewhat because of the clobbers, so I thought we could change the error return at the same time. I'm open to not changing it and using CR0[SO], but others liked the idea. Pro: it matches sc and vsyscall. Con: it's different from other common archs. Performnce-wise it would really be a wash -- cost of conditional branch is not the cmp but the mispredict. Thanks, Nick