From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/562 Path: news.gmane.org!not-for-mail From: Solar Designer Newsgroups: gmane.linux.lib.musl.general Subject: Re: tough choice on thread pointer initialization issue Date: Fri, 10 Feb 2012 23:12:09 +0400 Message-ID: <20120210191209.GA17416@openwall.com> References: <20120210025824.GA25414@brightrain.aerifal.cx> <20120210074002.GA13559@openwall.com> <20120210075818.GG146@brightrain.aerifal.cx> <20120210104252.GA14485@openwall.com> <20120210170015.GH146@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: dough.gmane.org 1328901138 8753 80.91.229.3 (10 Feb 2012 19:12:18 GMT) X-Complaints-To: usenet@dough.gmane.org NNTP-Posting-Date: Fri, 10 Feb 2012 19:12:18 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-563-gllmg-musl=m.gmane.org@lists.openwall.com Fri Feb 10 20:12:18 2012 Return-path: Envelope-to: gllmg-musl@plane.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1RvvtJ-0007Up-JX for gllmg-musl@plane.gmane.org; Fri, 10 Feb 2012 20:12:17 +0100 Original-Received: (qmail 12255 invoked by uid 550); 10 Feb 2012 19:12:17 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: Original-Received: (qmail 12247 invoked from network); 10 Feb 2012 19:12:17 -0000 Content-Disposition: inline In-Reply-To: <20120210170015.GH146@brightrain.aerifal.cx> User-Agent: Mutt/1.4.2.3i Xref: news.gmane.org gmane.linux.lib.musl.general:562 Archived-At: On Fri, Feb 10, 2012 at 12:00:15PM -0500, Rich Felker wrote: > On Fri, Feb 10, 2012 at 02:42:52PM +0400, Solar Designer wrote: > > All of these execute in 1000 cycles total as well. With "w" forms of > > the instructions there are extra prefixes, so I think these should > > better be avoided, even though there's no slowdown from them on this CPU. > > I had no idea it was even valid to use the non-w-prefix forms with > segment registers. Learned something new. Are the high bits just > discarded (when writing) and zeroed (when reading)? Yes. Frankly, I am not sure how portable this is exactly. The Linux kernel uses these short forms unconditionally (although there are also a few instances of "movw"), whereas glibc somehow uses them on 686+ only - see nptl/sysdeps/i386/tls.h vs. nptl/sysdeps/i386/i686/tls.h. The latter has this comment: /* Macros to load from and store into segment registers. We can use the 32-bit instructions. */ My guess is that this is one of those things that was always this way, but was only documented much later - starting with Pentium Pro maybe? We can download some PDFs from Intel to confirm when this appeared officially. I'd start with those for PPro. There were several things documented at about this time - e.g., the SALC instruction that was available since 8086 (including clones), but was only documented by Intel starting with Pentium Pro. glibc is probably too careful in limiting this to 686+. Well, I wouldn't be too surprised if some pre-686 CPU did not zero out the high bits on read from segment registers into 32-bit registers. If we're merely copying the value into another segment register, this does not matter, but for the non-zero test it does... Alexander