From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/3803 Path: news.gmane.org!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: ARM memcpy post-0.9.12-release thread Date: Fri, 2 Aug 2013 20:01:39 -0400 Message-ID: <20130803000139.GR221@brightrain.aerifal.cx> References: <20130731022631.GA6655@brightrain.aerifal.cx> <20130802204146.GO221@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: ger.gmane.org 1375488111 8995 80.91.229.3 (3 Aug 2013 00:01:51 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Sat, 3 Aug 2013 00:01:51 +0000 (UTC) Cc: Andre Renaud To: musl@lists.openwall.com Original-X-From: musl-return-3807-gllmg-musl=m.gmane.org@lists.openwall.com Sat Aug 03 02:01:53 2013 Return-path: Envelope-to: gllmg-musl@plane.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1V5PI8-0005ts-IM for gllmg-musl@plane.gmane.org; Sat, 03 Aug 2013 02:01:52 +0200 Original-Received: (qmail 3530 invoked by uid 550); 3 Aug 2013 00:01:51 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: Original-Received: (qmail 3522 invoked from network); 3 Aug 2013 00:01:51 -0000 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Xref: news.gmane.org gmane.linux.lib.musl.general:3803 Archived-At: On Sat, Aug 03, 2013 at 10:03:14AM +1200, Andre Renaud wrote: > Hi Rich, > > On 3 August 2013 08:41, Rich Felker wrote: > > Andre, do you have any input on this? (Cc'ing) > > > > Rich > > Sorry, I've been reading the emails, but haven't had a chance to get > back to the code. I don't really have an opinion on the gcc memcpy > issue, however I was still hopeful that we could come up with a > relatively clean mixed C/asm solution for the misaligned/non-congruent > copy scenario. Having said that, I haven't done anything on it yet. > > To be honest, although a solution probably exists, I doubt it's ever > going to be much better than the bionic code (with the exception of > possibly being less to read). I'm not sure about the "less to read" either. I would very much _like_ some generic C code for this, since the same basic strategy is applicable to all RISC-y archs with lots of registers but no misaligned memory access: 1. Read several aligned words. 2. Bitshift them with carry to adjust for the relative misalignment of the destination. 3. Write several aligned words. Unfortunately what this amounts to is N-1, where N is the alignment (4 for ARM, 8 for 64-bit-register archs), versions of the misaligned copy code, one for each value of (dest-src)%N. Oh, and you need separate cases for little and big endian too, since the bitshifts work with values rather than just representations. My guess is that at best we'll only get about 80% of the performance of the bionic asm, but I could be pleasantly surprised. What makes it nice is that this could get us acceptable memcpy performance on mips, powerpc, microblaze, etc. without having to write assembly for them all. I'll probably add the bionic asm for now, but I can't do it without first adding a way to disable it for "armeb". Rich