From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/6979 Path: news.gmane.org!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: [PATCH 1/2] x86_64/memset: simple optimizations Date: Tue, 10 Feb 2015 20:21:26 -0500 Message-ID: <20150211012126.GQ23507@brightrain.aerifal.cx> References: <1423589457-8407-1-git-send-email-vda.linux@googlemail.com> <20150210205047.GK23507@brightrain.aerifal.cx> <20150210213756.GM23507@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: ger.gmane.org 1423617704 18089 80.91.229.3 (11 Feb 2015 01:21:44 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Wed, 11 Feb 2015 01:21:44 +0000 (UTC) Cc: musl To: Denys Vlasenko Original-X-From: musl-return-6992-gllmg-musl=m.gmane.org@lists.openwall.com Wed Feb 11 02:21:44 2015 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1YLLzr-0007pc-RJ for gllmg-musl@m.gmane.org; Wed, 11 Feb 2015 02:21:43 +0100 Original-Received: (qmail 8177 invoked by uid 550); 11 Feb 2015 01:21:42 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: Original-Received: (qmail 8166 invoked from network); 11 Feb 2015 01:21:41 -0000 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:6979 Archived-At: On Wed, Feb 11, 2015 at 02:07:23AM +0100, Denys Vlasenko wrote: > On Tue, Feb 10, 2015 at 10:37 PM, Rich Felker wrote: > > OK. Based on some casual testing on my Celeron 847: > > > > - For small sizes, your patches make significant improvement, 20-30%. > > > > - For rep stosq path, the improvement is minimal (roughly 1-2 cycles). > > > > - Using 32-bit imul instead of 64-bit makes no difference at all. > > That's because Celeron 847 is a Sandy Bridge CPU. Only Intel's "big" > CPUs starting from Nehalem have fast (and large in transistor count) > integer multiplier capable of 3-cycle 64-bit multiply. > > Many other CPUs are worse, even Intel ones: Atoms are 13-cycle (!), > Silvermont: 5 cycles. AMD's Bulldozers: 6 cycles, Bobcat: 6-7, Jaguar: > 6, K10: 4 cycles. > > 32-bit imul is 3 or 4 cycles on all these CPUs (well, Atom has 5). Thanks for the info, and for the patches, which I just committed. Rich