From: Rich Felker <dalias@libc.org>
To: Denys Vlasenko <vda.linux@googlemail.com>
Cc: musl <musl@lists.openwall.com>
Subject: Re: [PATCH] x86_64/memset: use "small block" code for blocks up to 30 bytes long
Date: Sun, 15 Feb 2015 10:03:13 -0500 [thread overview]
Message-ID: <20150215150313.GO23507@brightrain.aerifal.cx> (raw)
In-Reply-To: <CAK1hOcPQ=mADeAUP3i-Xt3rvHmgUrVVoz2yUEOkUEYQ2xRVN2g@mail.gmail.com>
On Sun, Feb 15, 2015 at 03:07:06PM +0100, Denys Vlasenko wrote:
> On Sun, Feb 15, 2015 at 5:06 AM, Rich Felker <dalias@libc.org> wrote:
> >> The main change whose value I really question is the conditional
> >> widen_rax. If the value isn't used until a few cycles after the imul
> >> instruction, doing it unconditionally is probably cheaper than testing
> >> and branching even when the branch is predictable.
> >
> > To elaborate, simply replacing the unconditional imul with an
> > unconditional xor %eax,%eax in my best variant so far, I was only able
> > to save one cycle. So I don't see any way a test, branch, and
> > conditional imul could be less expensive than the unconditional imul.
>
> So imul elimination is a (tiny) win even on our CPUs, which happen
> to be the _fastest_ CPUs in regards to 64x64 imul (3 cycles).
No, it's a small (maybe you'd call it tiny) loss on them. That was my
point. It's only a tiny win when you rip out the conditional entirely
and just hard-code memset to always write zeros. (BTW, IIRC one OS had
a bug like that which went unnoticed for years... :)
> Just because we don't personally see a hit from 6-cycle imul of AMD CPUs,
> it does not mean people who do use those CPUs don't exist. Have heart...
Did you test the version I attached? I think there should be at least
4-5 cycles between when the imul is launched and when the result is
used, so I'm failing to see how the latency is a big deal.
Rich
next prev parent reply other threads:[~2015-02-15 15:03 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-13 16:39 Denys Vlasenko
2015-02-14 19:35 ` Rich Felker
2015-02-15 4:06 ` Rich Felker
2015-02-15 14:07 ` Denys Vlasenko
2015-02-15 15:03 ` Rich Felker [this message]
2015-02-15 21:44 ` Denys Vlasenko
2015-02-15 22:55 ` Rich Felker
2015-02-16 10:09 ` Denys Vlasenko
2015-02-16 15:12 ` Rich Felker
2015-02-16 17:36 ` Rich Felker
2015-02-17 13:08 ` Denys Vlasenko
2015-02-17 16:12 ` Rich Felker
2015-02-17 16:51 ` Denys Vlasenko
2015-02-17 17:30 ` Denys Vlasenko
2015-02-17 17:40 ` Rich Felker
2015-02-17 18:53 ` Denys Vlasenko
2015-02-17 21:12 ` Rich Felker
2015-02-18 9:05 ` Denys Vlasenko
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