fenv.s ARMv7 with clang

fenv.s ARMv7 with clang

[Kjell Braden]

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Hi,

I've attached a patch that allows to compile fenv.s when using clang 
targeting ARMv7. I haven't tried this with older architectures or other 
compilers, but clang refuses to compile MRC/MCR with cp10. Instead, it 
requires using VMSR/VMRS with FPSCR.

Best
Kjell

[-- Attachment #2: armv7-fenv.patch --]
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commit 817ffbe14ee0ff371c86a379239b31ec17c1b626
Author: Kjell Braden <kjell.braden@cased.de>
Date:   Tue Jul 14 17:20:06 2015 +0200

    fix fenv for ARMv7

diff --git a/src/fenv/armhf/fenv.s b/src/fenv/armhf/fenv.s
index 387234b..00cacee 100644
--- a/src/fenv/armhf/fenv.s
+++ b/src/fenv/armhf/fenv.s
@@ -1,17 +1,17 @@
 .global fegetround
 .type fegetround,%function
 fegetround:
-	mrc p10, 7, r0, cr1, cr0, 0
+	vmrs r0, FPSCR
 	and r0, r0, #0xc00000
 	bx lr
 
 .global __fesetround
 .type __fesetround,%function
 __fesetround:
-	mrc p10, 7, r3, cr1, cr0, 0
+	vmrs r3, FPSCR
 	bic r3, r3, #0xc00000
 	orr r3, r3, r0
-	mcr p10, 7, r3, cr1, cr0, 0
+	vmsr FPSCR, r3
 	mov r0, #0
 	bx lr
 
@@ -19,7 +19,7 @@ __fesetround:
 .type fetestexcept,%function
 fetestexcept:
 	and r0, r0, #0x1f
-	mrc p10, 7, r3, cr1, cr0, 0
+	vmrs r3, FPSCR
 	and r0, r0, r3
 	bx lr
 
@@ -27,9 +27,9 @@ fetestexcept:
 .type feclearexcept,%function
 feclearexcept:
 	and r0, r0, #0x1f
-	mrc p10, 7, r3, cr1, cr0, 0
+	vmrs r3, FPSCR
 	bic r3, r3, r0
-	mcr p10, 7, r3, cr1, cr0, 0
+	vmsr FPSCR, r3
 	mov r0, #0
 	bx lr
 
@@ -37,16 +37,16 @@ feclearexcept:
 .type feraiseexcept,%function
 feraiseexcept:
 	and r0, r0, #0x1f
-	mrc p10, 7, r3, cr1, cr0, 0
+	vmrs r3, FPSCR
 	orr r3, r3, r0
-	mcr p10, 7, r3, cr1, cr0, 0
+	vmsr FPSCR, r3
 	mov r0, #0
 	bx lr
 
 .global fegetenv
 .type fegetenv,%function
 fegetenv:
-	mrc p10, 7, r3, cr1, cr0, 0
+	vmrs r3, FPSCR
 	str r3, [r0]
 	mov r0, #0
 	bx lr
@@ -57,6 +57,6 @@ fesetenv:
 	cmn r0, #1
 	moveq r3, #0
 	ldrne r3, [r0]
-	mcr p10, 7, r3, cr1, cr0, 0
+	vmsr FPSCR, r3
 	mov r0, #0
 	bx lr

Re: fenv.s ARMv7 with clang

[Szabolcs Nagy]

* Kjell Braden <kjell.braden@cased.de> [2015-07-21 10:23:56 +0200]:
> I've attached a patch that allows to compile fenv.s when using clang
> targeting ARMv7. I haven't tried this with older architectures or other
> compilers, but clang refuses to compile MRC/MCR with cp10. Instead, it
> requires using VMSR/VMRS with FPSCR.
> 

there is a problem which i also have to fix in math/armhf/*.s

some armhf toolchains don't pass down -mfpu=vfp to the assembler,
they just add ".fpu vfp" directive to the asm when compiling c code,
so when you compile an asm file directly without the .fpu directive
the vfp instructions are rejected by gas.

the solution is either pass -mfpu=vfp* in the CFLAGS (but it needs
some amount of configure trickery) or add the .fpu directive to
these asm files.

asm for reading FPSCR (all have the same encoding):

.word 0xeef10a10       // always ok but not treated as an insn
mcr p10,7,r0,cp1,cp0,0 // should be always ok, deprecated?
fmrx r0,fpscr          // old mnemonics, needs vfp
vmrs r0,fpscr          // new mnemonics, needs vfp and binutils >=2.21

i think we should change all armhf asm to use the old mnemonics
(i think "unified assembler language" was introduced in armv7 and
vfpv3, but new binutils accepts both old and new mnemonics independently
of arm version) and add ".fpu vfp" if vfp instructions are used.

i will do these changes if there are no objections.

Re: fenv.s ARMv7 with clang

[Szabolcs Nagy]

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* Szabolcs Nagy <nsz@port70.net> [2015-07-21 15:08:25 +0200]:
> * Kjell Braden <kjell.braden@cased.de> [2015-07-21 10:23:56 +0200]:
> > I've attached a patch that allows to compile fenv.s when using clang
> > targeting ARMv7. I haven't tried this with older architectures or other
> > compilers, but clang refuses to compile MRC/MCR with cp10. Instead, it
> > requires using VMSR/VMRS with FPSCR.
> > 
> 
> there is a problem which i also have to fix in math/armhf/*.s
> 
> some armhf toolchains don't pass down -mfpu=vfp to the assembler,
> they just add ".fpu vfp" directive to the asm when compiling c code,
> so when you compile an asm file directly without the .fpu directive
> the vfp instructions are rejected by gas.
> 
> the solution is either pass -mfpu=vfp* in the CFLAGS (but it needs
> some amount of configure trickery) or add the .fpu directive to
> these asm files.
> 
> asm for reading FPSCR (all have the same encoding):
> 
> .word 0xeef10a10       // always ok but not treated as an insn
> mcr p10,7,r0,cp1,cp0,0 // should be always ok, deprecated?
> fmrx r0,fpscr          // old mnemonics, needs vfp
> vmrs r0,fpscr          // new mnemonics, needs vfp and binutils >=2.21
> 
> i think we should change all armhf asm to use the old mnemonics
> (i think "unified assembler language" was introduced in armv7 and
> vfpv3, but new binutils accepts both old and new mnemonics independently
> of arm version) and add ".fpu vfp" if vfp instructions are used.
> 
> i will do these changes if there are no objections.

attached a patch.

[-- Attachment #2: 0001-fix-armhf-asm-to-use-.fpu-vfp-and-robust-mnemonics.patch --]
[-- Type: text/x-diff, Size: 3790 bytes --]

From 9d72449f4d2216dd6eccad8f635157fb5799aed1 Mon Sep 17 00:00:00 2001
From: Szabolcs Nagy <nsz@port70.net>
Date: Tue, 21 Jul 2015 20:00:03 +0000
Subject: [PATCH] fix armhf asm to use .fpu vfp and robust mnemonics

(1) Some armhf toolchains (gcc built with --with-float=hard but
without --with-fpu=vfp*) do not pass -mfpu=vfp to the assembler. Such
toolchain can use VFP instructions when compiling C code because it
emits a .fpu vfp asm directive. Without the -mfpu option and the .fpu
directive the assembler rejects VFP instructions.

(2) New binutils/assemblers should support the old mnemonics (before
the unified assembler language was introduced) but an old toolchain
may not support the new ones.

(3) mrc/mcr p10 coprocessor mnemonics are deprecated by some
toolchains.

Changed VFP instructions to use old mnemonics, replaced mcr/mrc
with fmxr/fmrx and added .fpu vfp directive to all armhf asm with
VFP instructions. The generated code should not change on toolchains
that worked before.
---
---
 src/fenv/armhf/fenv.s  | 22 ++++++++++++----------
 src/math/armhf/fabs.s  |  3 ++-
 src/math/armhf/fabsf.s |  3 ++-
 src/math/armhf/sqrt.s  |  3 ++-
 src/math/armhf/sqrtf.s |  3 ++-
 5 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/src/fenv/armhf/fenv.s b/src/fenv/armhf/fenv.s
index 387234b..e447ca1 100644
--- a/src/fenv/armhf/fenv.s
+++ b/src/fenv/armhf/fenv.s
@@ -1,17 +1,19 @@
+.fpu vfp
+
 .global fegetround
 .type fegetround,%function
 fegetround:
-	mrc p10, 7, r0, cr1, cr0, 0
+	fmrx r0, fpscr
 	and r0, r0, #0xc00000
 	bx lr
 
 .global __fesetround
 .type __fesetround,%function
 __fesetround:
-	mrc p10, 7, r3, cr1, cr0, 0
+	fmrx r3, fpscr
 	bic r3, r3, #0xc00000
 	orr r3, r3, r0
-	mcr p10, 7, r3, cr1, cr0, 0
+	fmxr fpscr, r3
 	mov r0, #0
 	bx lr
 
@@ -19,7 +21,7 @@ __fesetround:
 .type fetestexcept,%function
 fetestexcept:
 	and r0, r0, #0x1f
-	mrc p10, 7, r3, cr1, cr0, 0
+	fmrx r3, fpscr
 	and r0, r0, r3
 	bx lr
 
@@ -27,9 +29,9 @@ fetestexcept:
 .type feclearexcept,%function
 feclearexcept:
 	and r0, r0, #0x1f
-	mrc p10, 7, r3, cr1, cr0, 0
+	fmrx r3, fpscr
 	bic r3, r3, r0
-	mcr p10, 7, r3, cr1, cr0, 0
+	fmxr fpscr, r3
 	mov r0, #0
 	bx lr
 
@@ -37,16 +39,16 @@ feclearexcept:
 .type feraiseexcept,%function
 feraiseexcept:
 	and r0, r0, #0x1f
-	mrc p10, 7, r3, cr1, cr0, 0
+	fmrx r3, fpscr
 	orr r3, r3, r0
-	mcr p10, 7, r3, cr1, cr0, 0
+	fmxr fpscr, r3
 	mov r0, #0
 	bx lr
 
 .global fegetenv
 .type fegetenv,%function
 fegetenv:
-	mrc p10, 7, r3, cr1, cr0, 0
+	fmrx r3, fpscr
 	str r3, [r0]
 	mov r0, #0
 	bx lr
@@ -57,6 +59,6 @@ fesetenv:
 	cmn r0, #1
 	moveq r3, #0
 	ldrne r3, [r0]
-	mcr p10, 7, r3, cr1, cr0, 0
+	fmxr fpscr, r3
 	mov r0, #0
 	bx lr
diff --git a/src/math/armhf/fabs.s b/src/math/armhf/fabs.s
index 2bdebff..e3b9018 100644
--- a/src/math/armhf/fabs.s
+++ b/src/math/armhf/fabs.s
@@ -1,6 +1,7 @@
+.fpu vfp
 .text
 .global fabs
 .type   fabs,%function
 fabs:
-	vabs.f64 d0, d0
+	fabsd d0, d0
 	bx lr
diff --git a/src/math/armhf/fabsf.s b/src/math/armhf/fabsf.s
index 35c720f..2b2e445 100644
--- a/src/math/armhf/fabsf.s
+++ b/src/math/armhf/fabsf.s
@@ -1,6 +1,7 @@
+.fpu vfp
 .text
 .global fabsf
 .type   fabsf,%function
 fabsf:
-	vabs.f32 s0, s0
+	fabss s0, s0
 	bx lr
diff --git a/src/math/armhf/sqrt.s b/src/math/armhf/sqrt.s
index 99fe64b..abda92f 100644
--- a/src/math/armhf/sqrt.s
+++ b/src/math/armhf/sqrt.s
@@ -1,6 +1,7 @@
+.fpu vfp
 .text
 .global sqrt
 .type   sqrt,%function
 sqrt:
-	vsqrt.f64 d0, d0
+	fsqrtd d0, d0
 	bx lr
diff --git a/src/math/armhf/sqrtf.s b/src/math/armhf/sqrtf.s
index 9ea519f..bbdea8e 100644
--- a/src/math/armhf/sqrtf.s
+++ b/src/math/armhf/sqrtf.s
@@ -1,6 +1,7 @@
+.fpu vfp
 .text
 .global sqrtf
 .type   sqrtf,%function
 sqrtf:
-	vsqrt.f32 s0, s0
+	fsqrts s0, s0
 	bx lr
-- 
2.4.1