From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/8315 Path: news.gmane.org!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: [PATCH] replace a mfence instruction by an xchg instruction Date: Sun, 16 Aug 2015 13:00:51 -0400 Message-ID: <20150816170051.GS31018@brightrain.aerifal.cx> References: <1439621420.9803.20.camel@dysnomia.u-strasbg.fr> <20150816162801.GR31018@brightrain.aerifal.cx> <1439743112.9803.40.camel@inria.fr> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: ger.gmane.org 1439744469 18026 80.91.229.3 (16 Aug 2015 17:01:09 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Sun, 16 Aug 2015 17:01:09 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-8327-gllmg-musl=m.gmane.org@lists.openwall.com Sun Aug 16 19:01:09 2015 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1ZR1Iw-0006uP-Nz for gllmg-musl@m.gmane.org; Sun, 16 Aug 2015 19:01:06 +0200 Original-Received: (qmail 15833 invoked by uid 550); 16 Aug 2015 17:01:04 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: Original-Received: (qmail 15815 invoked from network); 16 Aug 2015 17:01:03 -0000 Content-Disposition: inline In-Reply-To: <1439743112.9803.40.camel@inria.fr> User-Agent: Mutt/1.5.21 (2010-09-15) Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:8315 Archived-At: On Sun, Aug 16, 2015 at 06:38:32PM +0200, Jens Gustedt wrote: > Am Sonntag, den 16.08.2015, 12:28 -0400 schrieb Rich Felker: > > On Sat, Aug 15, 2015 at 08:51:41AM +0200, Jens Gustedt wrote: > > > according to the wisdom of the Internet, e.g > > > > > > https://peeterjoot.wordpress.com/2009/12/04/intel-memory-ordering-fence-instructions-and-atomic-operations/ > > > > > > a mfence instruction is about 3 times slower than an xchg instruction. > > > > I can't find where the article makes this claim. Could you point out > > what part you're referring to? > > I read this in the section that says "Performance comparsion". > > There it says something like "lock xchg" 16x baseline and "smfence" > 47-67 x baseline. But perhaps I am misinterpreting things. This is comparing an idiotic (and invalid, but maybe barely-working on x86) Dekker lock using mfence with a simple xchg-based lock. It's not comparing mfence to lock-xchg as barriers. Rich