From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9191 Path: news.gmane.org!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: [PATCH v3] Add PowerPC soft-float support Date: Mon, 25 Jan 2016 12:12:35 -0500 Message-ID: <20160125171235.GA238@brightrain.aerifal.cx> References: <1453724452-19211-1-git-send-email-nbd@openwrt.org> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: ger.gmane.org 1453741978 31193 80.91.229.3 (25 Jan 2016 17:12:58 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Mon, 25 Jan 2016 17:12:58 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-9204-gllmg-musl=m.gmane.org@lists.openwall.com Mon Jan 25 18:12:52 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1aNkhA-00012h-M0 for gllmg-musl@m.gmane.org; Mon, 25 Jan 2016 18:12:52 +0100 Original-Received: (qmail 21628 invoked by uid 550); 25 Jan 2016 17:12:50 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 21607 invoked from network); 25 Jan 2016 17:12:49 -0000 Content-Disposition: inline In-Reply-To: <1453724452-19211-1-git-send-email-nbd@openwrt.org> User-Agent: Mutt/1.5.21 (2010-09-15) Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:9191 Archived-At: On Mon, Jan 25, 2016 at 01:20:52PM +0100, Felix Fietkau wrote: > Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different > instruction set for floating point operations (SPE). > Executing regular PowerPC floating point instructions results in > "Illegal instruction" errors. > > Make it possible to run these devices in soft-float mode. If their fpu is ieee conforming (this is probably a big if) it should be possible for them to run in hard-float mode too, but the ABI is still the soft-float ABI since floating point args and return values get passed in GP registers. Just one question: > diff --git a/arch/powerpc/bits/fenv.h b/arch/powerpc/bits/fenv.h > index 2f722e6..c5a3e5c 100644 > --- a/arch/powerpc/bits/fenv.h > +++ b/arch/powerpc/bits/fenv.h > @@ -1,3 +1,7 @@ > +#ifdef _SOFT_FLOAT > +#define FE_ALL_EXCEPT 0 > +#define FE_TONEAREST 0 > +#else > #define FE_TONEAREST 0 > #define FE_TOWARDZERO 1 > #define FE_UPWARD 2 > @@ -24,6 +28,7 @@ Does the _SOFT_FLOAT macro accurately represent that the "soft float ABI" (float args/returns in GP registers) is being used, or is it only defined when floating point has been completely disabled? Aside from this question, the patch looks great. Thanks! Rich