From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9516 Path: news.gmane.org!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: [PATCH v3] Add PowerPC soft-float support Date: Sun, 6 Mar 2016 17:09:53 -0500 Message-ID: <20160306220952.GV9349@brightrain.aerifal.cx> References: <1453724452-19211-1-git-send-email-nbd@openwrt.org> <20160125171235.GA238@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: ger.gmane.org 1457302210 16619 80.91.229.3 (6 Mar 2016 22:10:10 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Sun, 6 Mar 2016 22:10:10 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-9529-gllmg-musl=m.gmane.org@lists.openwall.com Sun Mar 06 23:10:10 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1acgsL-0004eN-6V for gllmg-musl@m.gmane.org; Sun, 06 Mar 2016 23:10:09 +0100 Original-Received: (qmail 23701 invoked by uid 550); 6 Mar 2016 22:10:06 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 23677 invoked from network); 6 Mar 2016 22:10:05 -0000 Content-Disposition: inline In-Reply-To: <20160125171235.GA238@brightrain.aerifal.cx> User-Agent: Mutt/1.5.21 (2010-09-15) Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:9516 Archived-At: On Mon, Jan 25, 2016 at 12:12:35PM -0500, Rich Felker wrote: > On Mon, Jan 25, 2016 at 01:20:52PM +0100, Felix Fietkau wrote: > > Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different > > instruction set for floating point operations (SPE). > > Executing regular PowerPC floating point instructions results in > > "Illegal instruction" errors. > > > > Make it possible to run these devices in soft-float mode. > > If their fpu is ieee conforming (this is probably a big if) it should > be possible for them to run in hard-float mode too, but the ABI is > still the soft-float ABI since floating point args and return values > get passed in GP registers. Just one question: > > > diff --git a/arch/powerpc/bits/fenv.h b/arch/powerpc/bits/fenv.h > > index 2f722e6..c5a3e5c 100644 > > --- a/arch/powerpc/bits/fenv.h > > +++ b/arch/powerpc/bits/fenv.h > > @@ -1,3 +1,7 @@ > > +#ifdef _SOFT_FLOAT > > +#define FE_ALL_EXCEPT 0 > > +#define FE_TONEAREST 0 > > +#else > > #define FE_TONEAREST 0 > > #define FE_TOWARDZERO 1 > > #define FE_UPWARD 2 > > @@ -24,6 +28,7 @@ > > Does the _SOFT_FLOAT macro accurately represent that the "soft float > ABI" (float args/returns in GP registers) is being used, or is it only > defined when floating point has been completely disabled? > > Aside from this question, the patch looks great. Thanks! I've left this pending way too long so I'm just committing it, but I still do want to check out the situation with SPE. For now I'm going to add a configure test that will hopefully error out on SPE hard-float (because I don't think the current #ifdefs and sj/lj impl are valid to handle it, even though it may conceptually be -sf ABI compatible) and we can take that out and enable SPE hard-float later if it's actually ABI-compatible and we figure out the right #ifdefs. Rich