From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9718 Path: news.gmane.org!not-for-mail From: "dalias@libc.org" Newsgroups: gmane.linux.lib.musl.general Subject: Re: [PATCH] Fix atomic_arch.h for MIPS32 R6 Date: Mon, 21 Mar 2016 13:37:54 -0400 Message-ID: <20160321173754.GC21636@brightrain.aerifal.cx> References: Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: ger.gmane.org 1458581895 21491 80.91.229.3 (21 Mar 2016 17:38:15 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Mon, 21 Mar 2016 17:38:15 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-9731-gllmg-musl=m.gmane.org@lists.openwall.com Mon Mar 21 18:38:13 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1ai3mP-0006es-4y for gllmg-musl@m.gmane.org; Mon, 21 Mar 2016 18:38:13 +0100 Original-Received: (qmail 1325 invoked by uid 550); 21 Mar 2016 17:38:09 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 32748 invoked from network); 21 Mar 2016 17:38:07 -0000 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:9718 Archived-At: On Mon, Mar 21, 2016 at 06:03:47AM +0000, Jaydeep Patil wrote: > Hi Rich, > > The arch/mips/atomic_arch.h uses MIPS2 opcode for LL and SC > instructions. Opcodes of these instructions differ on MIPSR6. Does this mean MIPSR6 is an incompatible ISA that can't run normal MIPS binaries? If so that's a messy situation we need to find a way to deal with; if the difference is just LLSC though then perhaps the kernel's emulation handles it (albeit very slowly). It would be helpful if you could provide a link to the documentation of this issue (different opcodes). > Refer to https://github.com/JaydeepIMG/musl-1/tree/fix_atomic_for_MIPS32_R6 for the patch. > > >From 63428cfc5dfa75d2771ba8205067c438942e1a60 Mon Sep 17 00:00:00 2001 > From: Jaydeep Patil > Date: Mon, 21 Mar 2016 06:00:39 +0000 > Subject: [PATCH] Fix for opcodes of LL/SC instructions for MIPSR6 > > --- > arch/mips/atomic_arch.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h > index ce2823b..16b1542 100644 > --- a/arch/mips/atomic_arch.h > +++ b/arch/mips/atomic_arch.h > @@ -3,9 +3,13 @@ static inline int a_ll(volatile int *p) > { > int v; > __asm__ __volatile__ ( > +#if __mips_isa_rev < 6 > ".set push ; .set mips2\n\t" > +#endif > "ll %0, %1" > +#if __mips_isa_rev < 6 > "\n\t.set pop" > +#endif I think just the .set mips2 could be inside #ifdef with the push/pop always used; that produces less #ifdef clutter. But first we need to figure out the above issues. Rich