Re: [PATCH] Fix atomic_arch.h for MIPS32 R6

[Rich Felker <dalias@libc.org>]

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On Wed, Mar 30, 2016 at 10:29:26AM -0400, Rich Felker wrote:
> Since I've done most of the thinking about the above issues already
> and have a patch for some of them, let me prepare a complete patch and
> send it to the list for you to check and make sure it meets your needs
> for r6. I should be able to prepare it very quickly. Then we can look
> at applying the same changes to the n32 port and reviewing it.

Can you see if the attached patch works for you? It not only adds r6
support but improves support for non-baseline (i.e. > mips1) ISA
levels by optimizing out the unnecessary .set's (which hurt gcc's
inlining, because gcc is dumb about them) and lifts the $3 register
restriction on rdhwr for ISA levels where the instructions are known
to be available natively.

Rich

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diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h
index ce2823b..1248d17 100644
--- a/arch/mips/atomic_arch.h
+++ b/arch/mips/atomic_arch.h
@@ -1,12 +1,24 @@
+#if __mips_isa_rev < 6
+#define LLSC_M "m"
+#else
+#define LLSC_M "ZC"
+#endif
+
 #define a_ll a_ll
 static inline int a_ll(volatile int *p)
 {
 	int v;
+#if __mips < 2
 	__asm__ __volatile__ (
 		".set push ; .set mips2\n\t"
 		"ll %0, %1"
 		"\n\t.set pop"
 		: "=r"(v) : "m"(*p));
+#else
+	__asm__ __volatile__ (
+		"ll %0, %1"
+		: "=r"(v) : LLSC_M(*p));
+#endif
 	return v;
 }
 
@@ -14,26 +26,33 @@ static inline int a_ll(volatile int *p)
 static inline int a_sc(volatile int *p, int v)
 {
 	int r;
+#if __mips < 2
 	__asm__ __volatile__ (
 		".set push ; .set mips2\n\t"
 		"sc %0, %1"
 		"\n\t.set pop"
 		: "=r"(r), "=m"(*p) : "0"(v) : "memory");
+#else
+	__asm__ __volatile__ (
+		"sc %0, %1"
+		: "=r"(r), "="LLSC_M(*p) : "0"(v) : "memory");
+#endif
 	return r;
 }
 
 #define a_barrier a_barrier
 static inline void a_barrier()
 {
+#if __mips < 2
 	/* mips2 sync, but using too many directives causes
 	 * gcc not to inline it, so encode with .long instead. */
 	__asm__ __volatile__ (".long 0xf" : : : "memory");
-#if 0
-	__asm__ __volatile__ (
-		".set push ; .set mips2 ; sync ; .set pop"
-		: : : "memory");
+#else
+	__asm__ __volatile__ ("sync" : : : "memory");
 #endif
 }
 
 #define a_pre_llsc a_barrier
 #define a_post_llsc a_barrier
+
+#undef LLSC_M
diff --git a/arch/mips/pthread_arch.h b/arch/mips/pthread_arch.h
index 8a49965..e581265 100644
--- a/arch/mips/pthread_arch.h
+++ b/arch/mips/pthread_arch.h
@@ -1,12 +1,11 @@
 static inline struct pthread *__pthread_self()
 {
-#ifdef __clang__
-	char *tp;
-	__asm__ __volatile__ (".word 0x7c03e83b ; move %0, $3" : "=r" (tp) : : "$3" );
-#else
+#if __mips_isa_rev < 2
 	register char *tp __asm__("$3");
-	/* rdhwr $3,$29 */
 	__asm__ __volatile__ (".word 0x7c03e83b" : "=r" (tp) );
+#else
+	char *tp;
+	__asm__ __volatile__ ("rdhwr %0, $29" : "=r" (tp) );
 #endif
 	return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
 }
diff --git a/arch/mips/reloc.h b/arch/mips/reloc.h
index 8c52df0..b3d59a4 100644
--- a/arch/mips/reloc.h
+++ b/arch/mips/reloc.h
@@ -1,5 +1,11 @@
 #include <endian.h>
 
+#if __mips_isa_rev >= 6
+#define ISA_SUFFIX "r6"
+#else
+#define ISA_SUFFIX ""
+#endif
+
 #if __BYTE_ORDER == __LITTLE_ENDIAN
 #define ENDIAN_SUFFIX "el"
 #else
@@ -12,7 +18,7 @@
 #define FP_SUFFIX ""
 #endif
 
-#define LDSO_ARCH "mips" ENDIAN_SUFFIX FP_SUFFIX
+#define LDSO_ARCH "mips" ISA_SUFFIX ENDIAN_SUFFIX FP_SUFFIX
 
 #define TPOFF_K (-0x7000)
 
diff --git a/arch/mips64/atomic_arch.h b/arch/mips64/atomic_arch.h
index b468fd9..d0f8b4a 100644
--- a/arch/mips64/atomic_arch.h
+++ b/arch/mips64/atomic_arch.h
@@ -1,10 +1,16 @@
+#if __mips_isa_rev < 6
+#define LLSC_M "m"
+#else
+#define LLSC_M "ZC"
+#endif
+
 #define a_ll a_ll
 static inline int a_ll(volatile int *p)
 {
 	int v;
 	__asm__ __volatile__ (
 		"ll %0, %1"
-		: "=r"(v) : "m"(*p));
+		: "=r"(v) : LLSC_M(*p));
 	return v;
 }
 
@@ -14,7 +20,7 @@ static inline int a_sc(volatile int *p, int v)
 	int r;
 	__asm__ __volatile__ (
 		"sc %0, %1"
-		: "=r"(r), "=m"(*p) : "0"(v) : "memory");
+		: "=r"(r), "="LLSC_M(*p) : "0"(v) : "memory");
 	return r;
 }
 
@@ -24,7 +30,7 @@ static inline void *a_ll_p(volatile void *p)
 	void *v;
 	__asm__ __volatile__ (
 		"lld %0, %1"
-		: "=r"(v) : "m"(*(void *volatile *)p));
+		: "=r"(v) : LLSC_M(*(void *volatile *)p));
 	return v;
 }
 
@@ -34,17 +40,17 @@ static inline int a_sc_p(volatile void *p, void *v)
 	long r;
 	__asm__ __volatile__ (
 		"scd %0, %1"
-		: "=r"(r), "=m"(*(void *volatile *)p) : "0"(v) : "memory");
+		: "=r"(r), "="LLSC_M(*(void *volatile *)p) : "0"(v) : "memory");
 	return r;
 }
 
 #define a_barrier a_barrier
 static inline void a_barrier()
 {
-	/* mips2 sync, but using too many directives causes
-	 * gcc not to inline it, so encode with .long instead. */
-	__asm__ __volatile__ (".long 0xf" : : : "memory");
+	__asm__ __volatile__ ("sync" : : : "memory");
 }
 
 #define a_pre_llsc a_barrier
 #define a_post_llsc a_barrier
+
+#undef LLSC_M
diff --git a/arch/mips64/pthread_arch.h b/arch/mips64/pthread_arch.h
index b42edbe..e581265 100644
--- a/arch/mips64/pthread_arch.h
+++ b/arch/mips64/pthread_arch.h
@@ -1,11 +1,11 @@
 static inline struct pthread *__pthread_self()
 {
-#ifdef __clang__
-	char *tp;
-	__asm__ __volatile__ (".word 0x7c03e83b ; move %0, $3" : "=r" (tp) : : "$3" );
-#else
+#if __mips_isa_rev < 2
 	register char *tp __asm__("$3");
 	__asm__ __volatile__ (".word 0x7c03e83b" : "=r" (tp) );
+#else
+	char *tp;
+	__asm__ __volatile__ ("rdhwr %0, $29" : "=r" (tp) );
 #endif
 	return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
 }
diff --git a/arch/mips64/reloc.h b/arch/mips64/reloc.h
index 5933147..bbd9bd9 100644
--- a/arch/mips64/reloc.h
+++ b/arch/mips64/reloc.h
@@ -4,6 +4,12 @@
 #define _GNU_SOURCE
 #include <endian.h>
 
+#if __mips_isa_rev >= 6
+#define ISA_SUFFIX "r6"
+#else
+#define ISA_SUFFIX ""
+#endif
+
 #if __BYTE_ORDER == __LITTLE_ENDIAN
 #define ENDIAN_SUFFIX "el"
 #else
@@ -16,7 +22,7 @@
 #define FP_SUFFIX ""
 #endif
 
-#define LDSO_ARCH "mips64" ENDIAN_SUFFIX FP_SUFFIX
+#define LDSO_ARCH "mips64" ISA_SUFFIX ENDIAN_SUFFIX FP_SUFFIX
 
 #define TPOFF_K (-0x7000)
 
diff --git a/configure b/configure
index 213a825..969671d 100755
--- a/configure
+++ b/configure
@@ -612,11 +612,13 @@ trycppif __AARCH64EB__ "$t" && SUBARCH=${SUBARCH}_be
 fi
 
 if test "$ARCH" = "mips" ; then
+trycppif "__mips_isa_rev >= 6" "$t" && SUBARCH=${SUBARCH}r6
 trycppif "_MIPSEL || __MIPSEL || __MIPSEL__" "$t" && SUBARCH=${SUBARCH}el
 trycppif __mips_soft_float "$t" && SUBARCH=${SUBARCH}-sf
 fi
 
 if test "$ARCH" = "mips64" ; then
+trycppif "__mips_isa_rev >= 6" "$t" && SUBARCH=${SUBARCH}r6
 trycppif "_MIPSEL || __MIPSEL || __MIPSEL__" "$t" && SUBARCH=${SUBARCH}el
 trycppif __mips_soft_float "$t" && SUBARCH=${SUBARCH}-sf
 fi