From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/10449 Path: news.gmane.org!.POSTED!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: [J-core] Aligned copies and cacheline conflicts? Date: Wed, 14 Sep 2016 20:34:51 -0400 Message-ID: <20160915003451.GC15995@brightrain.aerifal.cx> References: <0c256cb1-d0fa-9a5a-3976-b7ef545c1827@landley.net> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: blaine.gmane.org 1473899718 30481 195.159.176.226 (15 Sep 2016 00:35:18 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Thu, 15 Sep 2016 00:35:18 +0000 (UTC) User-Agent: Mutt/1.5.21 (2010-09-15) Cc: "j-core@j-core.org" , musl@lists.openwall.com To: Rob Landley Original-X-From: musl-return-10462-gllmg-musl=m.gmane.org@lists.openwall.com Thu Sep 15 02:35:14 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1bkKe1-0007AK-0X for gllmg-musl@m.gmane.org; Thu, 15 Sep 2016 02:35:13 +0200 Original-Received: (qmail 3540 invoked by uid 550); 15 Sep 2016 00:35:11 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 3508 invoked from network); 15 Sep 2016 00:35:09 -0000 Content-Disposition: inline In-Reply-To: <0c256cb1-d0fa-9a5a-3976-b7ef545c1827@landley.net> Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:10449 Archived-At: On Tue, Sep 13, 2016 at 07:21:58PM -0500, Rob Landley wrote: > There was a discussion at one point about how reading from and writing > to an alised cache line (anything at an 8k offset) would cause horrible > performance (the write cacheline evicting the read cacheline and vice > versa), how this was a more common problem than 1 in 256 because things > are often page aligned, and how a workaround was to have memcpy read > data into 8 registers and then write it out again from those 8 registers > to avoid the ping-ping. > > Question: did that memcpy change actually go into musl and the kernel? > (Seems like both would need it...) If so, what do I have to make sure > I've pulled to get them? This has not gone upstream yet mainly because: 1) I'm not sure if it's a good idea for other archs that use the generic C memcpy. 2) It would be a lot of extra code to handle the misaligned-mod-4 cases this way as well, and unlikely to help much anyway since this case doesn't arise from page alignment, so it's not clear if I should do this case too. I could put a fork of memcpy.c in sh/memcpy.c and work on it there and only merge it back to the shared one if others test it on other archs and find it beneficial (or at least not harmful). Rich