From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/10787 Path: news.gmane.org!.POSTED!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: cortex-m support? Date: Fri, 9 Dec 2016 01:33:27 -0500 Message-ID: <20161209063327.GR1555@brightrain.aerifal.cx> References: <04e5a294-719e-8029-704f-a57d1ec935b0@landley.net> <20161208211116.GO1555@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="xHFwDpU9dbj6ez1V" X-Trace: blaine.gmane.org 1481265222 20999 195.159.176.226 (9 Dec 2016 06:33:42 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Fri, 9 Dec 2016 06:33:42 +0000 (UTC) User-Agent: Mutt/1.5.21 (2010-09-15) To: musl@lists.openwall.com Original-X-From: musl-return-10800-gllmg-musl=m.gmane.org@lists.openwall.com Fri Dec 09 07:33:39 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1cFEkV-0004oQ-22 for gllmg-musl@m.gmane.org; Fri, 09 Dec 2016 07:33:39 +0100 Original-Received: (qmail 8079 invoked by uid 550); 9 Dec 2016 06:33:41 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 8061 invoked from network); 9 Dec 2016 06:33:40 -0000 Content-Disposition: inline In-Reply-To: <20161208211116.GO1555@brightrain.aerifal.cx> Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:10787 Archived-At: --xHFwDpU9dbj6ez1V Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Dec 08, 2016 at 04:11:16PM -0500, Rich Felker wrote: > On Tue, Dec 06, 2016 at 11:52:29PM -0600, Rob Landley wrote: > > Added support for the Cortex-M. > > ------------------------------------------------------------------------ > > Index: src/internal/arm/syscall.s > > =================================================================== > > --- src/internal/arm/syscall.s (revision 4919) > > +++ src/internal/arm/syscall.s (revision 4920) > > @@ -11,5 +11,6 @@ > > svc 0 > > ldmfd sp!,{r4,r5,r6,r7} > > tst lr,#1 > > + it eq > > moveq pc,lr > > bx lr > > There's a gas option -Wa,-mimplicit-it=always that will make these > kind of changes unnecessary. I think it's preferable to just have > musl's configure always add that option when targeting arm if it's > accepted by the toolchain. Otherwise new code might get added without > checking that it builds as thumb. I dug up the changes I made to get it to build (not run; atomics.s is broken) as thumb-only; see attached. Note that the atomics.s part of the diff actively breaks the code so that it won't work even as arm code. I'll see if I can come up with a good solution for the atomics. One thing I do need to know is how the thread pointer is supposed to be read on cortex-m, since afaik the coprocessor register normally used does not exist. Does the kernel trap and emulate the coprocessor register, or is there some other mechanism that must be used? Rich --xHFwDpU9dbj6ez1V Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="thumb.diff" diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s index e28d8f3..6191ab2 100644 --- a/src/setjmp/arm/longjmp.s +++ b/src/setjmp/arm/longjmp.s @@ -8,7 +8,9 @@ longjmp: mov ip,r0 movs r0,r1 moveq r0,#1 - ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} + ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp} + ldmia ip!, {r2,lr} + mov sp,r2 adr r1,1f ldr r2,1f diff --git a/src/setjmp/arm/setjmp.s b/src/setjmp/arm/setjmp.s index 8779163..c6fe1bb 100644 --- a/src/setjmp/arm/setjmp.s +++ b/src/setjmp/arm/setjmp.s @@ -9,7 +9,9 @@ __setjmp: _setjmp: setjmp: mov ip,r0 - stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} + stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp} + mov r2,sp + stmia ip!,{r2,lr} mov r0,#0 adr r1,1f diff --git a/src/string/arm/memcpy.c b/src/string/arm/memcpy.c index 041614f..f703c9b 100644 --- a/src/string/arm/memcpy.c +++ b/src/string/arm/memcpy.c @@ -1,3 +1,3 @@ -#if __ARMEB__ +#if __ARMEB__ || __thumb__ #include "../memcpy.c" #endif diff --git a/src/string/arm/memcpy_le.S b/src/string/arm/memcpy_le.S index 4db4844..9cfbcb2 100644 --- a/src/string/arm/memcpy_le.S +++ b/src/string/arm/memcpy_le.S @@ -1,4 +1,4 @@ -#ifndef __ARMEB__ +#if !__ARMEB__ && !__thumb__ /* * Copyright (C) 2008 The Android Open Source Project diff --git a/src/thread/arm/atomics.s b/src/thread/arm/atomics.s index 673fc03..380f714 100644 --- a/src/thread/arm/atomics.s +++ b/src/thread/arm/atomics.s @@ -6,7 +6,7 @@ .type __a_barrier,%function __a_barrier: ldr ip,1f - ldr ip,[pc,ip] + //ldr ip,[pc,ip] add pc,pc,ip 1: .word __a_barrier_ptr-1b .global __a_barrier_dummy @@ -40,7 +40,7 @@ __a_barrier_v7: .type __a_cas,%function __a_cas: ldr ip,1f - ldr ip,[pc,ip] + //ldr ip,[pc,ip] add pc,pc,ip 1: .word __a_cas_ptr-1b .global __a_cas_dummy @@ -85,7 +85,7 @@ __aeabi_read_tp: .type __a_gettp,%function __a_gettp: ldr r0,1f - ldr r0,[pc,r0] + //ldr r0,[pc,r0] add pc,pc,r0 1: .word __a_gettp_ptr-1b .global __a_gettp_dummy --xHFwDpU9dbj6ez1V--