From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/11212 Path: news.gmane.org!.POSTED!not-for-mail From: "dalias@libc.org" Newsgroups: gmane.linux.lib.musl.general Subject: Re: [MUSL] microMIPS32R2 O32 port Date: Thu, 6 Apr 2017 12:18:04 -0400 Message-ID: <20170406161804.GM17319@brightrain.aerifal.cx> References: Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: blaine.gmane.org 1491495500 9138 195.159.176.226 (6 Apr 2017 16:18:20 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Thu, 6 Apr 2017 16:18:20 +0000 (UTC) User-Agent: Mutt/1.5.21 (2010-09-15) To: musl@lists.openwall.com Original-X-From: musl-return-11227-gllmg-musl=m.gmane.org@lists.openwall.com Thu Apr 06 18:18:17 2017 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1cwA6v-0001nL-Qt for gllmg-musl@m.gmane.org; Thu, 06 Apr 2017 18:18:13 +0200 Original-Received: (qmail 9243 invoked by uid 550); 6 Apr 2017 16:18:17 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 9225 invoked from network); 6 Apr 2017 16:18:16 -0000 Content-Disposition: inline In-Reply-To: Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:11212 Archived-At: On Wed, Apr 05, 2017 at 06:33:01AM +0000, Jaydeep Patil wrote: > Hi Rich, > > Please refer to > https://github.com/JaydeepIMG/musl-1/tree/micromips32r2_v1 for > microMIPS32R2 O32 port. I have also attached the patch > (microMIPS32R2_v1_port.patch) for your reference. > Could you please review it? Some important first questions: Is micromips an ISA level or a new ISA? This is the same question as last time with MIPS r6 and the answer was not obvious and seemingly intentionally obscured by the official documentation. The answer is important to how we approach supporting it. Do cpus that support micromips also support plain mips? Is it like thumb where arm/thumb code can be linked together and call into one another in the same process, or are they different modes? Once we answer those questions, can you provide justifications for the proposed changes? From your patches it looks like branch delay slots don't exist in micromips mode. There may be other differences too; I didn't read it in detail. Rather than add a bunch of ifdefs I'd rather figure out how we can generalize the code so that it's compatible with both. This is what was done on arm when making it so the asm can be compiled as thumb2. Rich