From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/11255 Path: news.gmane.org!.POSTED!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: [MUSL] microMIPS32R2 O32 port Date: Fri, 21 Apr 2017 09:26:50 -0400 Message-ID: <20170421132650.GD17319@brightrain.aerifal.cx> References: <20170406161804.GM17319@brightrain.aerifal.cx> <20170407141941.GQ17319@brightrain.aerifal.cx> <20170412192535.GG2082@port70.net> <20170412202721.GY17319@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Trace: blaine.gmane.org 1492781227 16029 195.159.176.226 (21 Apr 2017 13:27:07 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Fri, 21 Apr 2017 13:27:07 +0000 (UTC) User-Agent: Mutt/1.5.21 (2010-09-15) Cc: Andre McCurdy , "musl@lists.openwall.com" To: Jaydeep Patil Original-X-From: musl-return-11270-gllmg-musl=m.gmane.org@lists.openwall.com Fri Apr 21 15:27:02 2017 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1d1YaT-00041U-MM for gllmg-musl@m.gmane.org; Fri, 21 Apr 2017 15:27:01 +0200 Original-Received: (qmail 20086 invoked by uid 550); 21 Apr 2017 13:27:05 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 20046 invoked from network); 21 Apr 2017 13:27:04 -0000 Content-Disposition: inline In-Reply-To: Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:11255 Archived-At: On Thu, Apr 13, 2017 at 04:29:10AM +0000, Jaydeep Patil wrote: > Hi, > > With this branch (micromips32r2_v2) we are supporting microMIPS > cores that co-exist with MIPS. The MUSL library must be built with > -minterlink-compressed option as there are couple of hand-written > MIPS only functions. For microMIPS only cores we will create a > different subarch. I don't think there's any indication yet that a different subarch is appropriate for micromips-only cores. This would only be the case if they are somehow ABI-incompatible with normal mips. If it would be possible to run binaries that were built for micromips only on a cpu core that supports both, using a libc.so that was built either for plain mips or micromips or a mix, then for our purposes it's the same arch, just a different ISA level/profile. Rich > >-----Original Message----- > >From: Andre McCurdy [mailto:armccurdy@gmail.com] > >Sent: 13 April 2017 AM 03:17 > >To: musl@lists.openwall.com > >Cc: Jaydeep Patil > >Subject: Re: [musl] [MUSL] microMIPS32R2 O32 port > > > >On Wed, Apr 12, 2017 at 1:27 PM, Rich Felker wrote: > >> On Wed, Apr 12, 2017 at 09:25:35PM +0200, Szabolcs Nagy wrote: > >>> * Jaydeep Patil [2017-04-12 11:54:10 +0000]: > >>> > Hi Rich, > >>> > > >>> > We can reuse existing MIPS code for microMIPS. There are places where > >we read from $ra must be compiled for MIPS. > >>> > Please refer to https://github.com/JaydeepIMG/musl- > >1/tree/micromips32r2_v2 for modifications. > >>> > > >>> > >>> is micromips a different encoding for mips instructions that works on > >>> some cpus but not others? > >> > >> Yes, it's something like thumb or thumb2 on arm, or the riscv > >> compressed isa. What I'm not clear on is whether there are > >> micromips-only cpu models that can't execute normal mips. > > > >According to: > > > > https://imagination-technologies-cloudfront- > >assets.s3.amazonaws.com/documentation/MIPS_Architecture_microMIPS32 > >_InstructionSet_AFP_P_MD00582_06.04.pdf > > > >"microMIPS is also an alternative to the MIPS® instruction encoding and can > >be implemented in parallel or stand-alone." > > > >"If only one ISA mode exists (either MIPS or microMIPS) then this mode > >switch mechanism does not exist" > > > >> If so we probably need the ability to build musl as micromips, but as > >> long as cpus which support both support interworking (calls between > >> the two type of code in the same process) reasonably, I don't think > >> there's any reason to consider it a different subarch. > >> > >> If not (that is, if all cpus that support micromips also support the > >> normal mips isa) then I fail to see why there's any need to compile > >> musl's asm files as micromips. They're not size or performance > >> bottlenecks. > >> > >> Rich