From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/12559 Path: news.gmane.org!.POSTED!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: clz instruction is unavailable for Thumb1 Date: Tue, 27 Feb 2018 20:01:10 -0500 Message-ID: <20180228010110.GS1436@brightrain.aerifal.cx> References: <1799b81c-10d6-c2ac-4411-6ee9808f2356@codeaurora.org> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: blaine.gmane.org 1519779564 21664 195.159.176.226 (28 Feb 2018 00:59:24 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Wed, 28 Feb 2018 00:59:24 +0000 (UTC) User-Agent: Mutt/1.5.21 (2010-09-15) To: musl@lists.openwall.com Original-X-From: musl-return-12575-gllmg-musl=m.gmane.org@lists.openwall.com Wed Feb 28 01:59:20 2018 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1eqq5X-00054l-Hy for gllmg-musl@m.gmane.org; Wed, 28 Feb 2018 01:59:19 +0100 Original-Received: (qmail 32333 invoked by uid 550); 28 Feb 2018 01:01:23 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 32303 invoked from network); 28 Feb 2018 01:01:22 -0000 Content-Disposition: inline In-Reply-To: Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:12559 Archived-At: On Tue, Feb 27, 2018 at 04:37:15PM -0800, Andre McCurdy wrote: > On Tue, Feb 27, 2018 at 4:03 PM, Zhao, Weiming wrote: > > In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not > > sufficient. > > > > for example, for armv6-m, it only support Thumb1, which doesn't include clz. > > > > Suggest to check if it's building for thumb1: > > Musl does not currently support Thumb 1. I forget what the situation with v6-m is, and whether/how it could be supportable. Is it really thumb1 or some thumb2 subset that fills deficiencies? My recollection was that thumb1 lacks atomics, barriers, thread-pointer loading, and maybe even syscalls, and since the kuser_helper addresses are arm addresses, you can't even use them to get the missing functionality. Rich > > diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h > > index c5c56f8..e3cb66a 100644 > > --- a/arch/arm/atomic_arch.h > > +++ b/arch/arm/atomic_arch.h > > @@ -82,7 +82,7 @@ static inline void a_crash() > > : : : "memory"); > > } > > > > -#if __ARM_ARCH >= 5 > > +#if __ARM_ARCH >= 5 && !(defined(__thumb__) && !defined(__thumb2)) > > > > > > > > -- > > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by > > The Linux Foundation > >